SynaptiCAD has released an updated version of WaveFormer Pro, a tool for analyzing timing diagrams and translating digital and analog waveforms between simulators and test equipment. The new version supports importing and exporting digital and analog waveforms to the latest Agilent and Tektronix logic analyzers and mixed-signal oscilloscopes. WaveFormer also supports importing timing information from the Mentor Graphic's Hyperlynx board-level tim...

SynaptiCAD now has new versions of HDL Work's IO Checker that will verify that signal names used in the FPGA are connected to the appropriate signals on the PCB. Additionally it verifies the voltage values connected to the FPGA power and reference pins.

SynaptiCAD has released an updated version of it's industry-leading timing diagram editor family that simplifies creating the Synopsys Design Constraint files used to define the timing requirements for FPGA synthesis tools. New versions of Timing Diagrammer Pro, WaveFormer Pro, and DataSheet Pro enable designers to automatically generate SDC commands from timing diagram data extracted from IC data sheets.

SynaptiCAD has upgraded the V2V tools that translate bidirectionally between Verilog and VHDL source code. These translators are primarily aimed at converting behavioral and/or RTL-level code and are most often used when a designer has received IP in another language than his preferred design language.

SynaptiCAD has recently released an updated version of their Verilog simulator, VeriLogger Extreme. The new version supports compiling source files to symbolic libraries, enabling faster compiles of designs that share a common set of source files such as ASIC/FPGA libraries.

SynaptiCAD has released an updated version of WaveViewer, a free viewer for digital and analog waveforms. Waveform formats supported by WaveViewer include VCD/EVCD, SPICE CSDF/TRN, Synopsys TimeMill, Agilent and Tektronix logic analyzer data and mixed-signal oscilloscope data, SynaptiCAD's compressed binary format (BTIM), and many other common formats produced by EDA tools. The viewer also supports color syntax highlighted editing for VHDL, Veril...

SynaptiCAD's has updated BugHunter, it's graphical test bench generator and HDL debugger, to add support for SystemC simulations. Standalone SystemC and mixed SystemC/Verilog/VHDL simulations can be compiled and debugged under the BugHunter GUI. The new environment simplifies compiling regular C++ applications in conjunction with an HDL simulation as well (for example, to compile a PLI-based application loaded by a Verilog simulator). The new ver...

SynaptiCAD has released a new version of TestBencher Pro, a VHDL and Verilog system-level testbench generation software that dramatically simplifies the process of creating and applying random bus transactions to RTL and gate-level models. The new version also simplfies creation of testbenches that reside in a different compiled library from the design being tested. TestBencher includes an updated version of SynaptiCAD's graphical HDL debugger, B...

SynaptiCAD has released an updated version of it's VHDL and Verilog testbench generation and debugging tool, BugHunter Pro, with support for 64-bit versions of Mentor Graphics ModelSim and Cadence Incisive simulators. Other new features include faster waveform capture (so simulations run 8x faster while being debugged), new methods for fast searching through the design hierarchy tree, support for capturing waveform data from VHDL types such as e...

SynaptiCAD’s Verilog netlist editor, Gates-on-the-Fly (GOF), has recently been updated to support easy correction of logic equivalence failures introduced during modifications to post-synthesis netlists, using equivalence check reports from either Cadence’s Conformal LEC or Synopsys’s Formality. SynaptiCAD has also published a white paper that describes how the updated GOF was used to find and fix failures identified by Cadence’s Conforma...

WaveFormer Lite Generates Mixed Signal HDL Test Benches for all FPGA design flows SynaptiCAD has just released a major upgrade to WaveFormer Lite, it's entry level tool for generating VHDL and Verilog test benches graphically from timing diagrams drawn by the user. Previously only available as part of the Actel Libero package, WaveFormer Lite can now be purchased directly from SynaptiCAD. WaveFormer Lite generates native VHDL and Verilog testbenc...

SynaptiCAD has released an updated version of VeriLogger Extreme, a compiled-code Verilog simulation and debugging environment, that adds support for encrypted IP models from all the major ASIC/FPGA vendors. VeriLogger supports both binary-encrypted SmartModels based on the common SWIFT-based standard and the more recent encrypted source-code format (sometimes referred to as protected envelopes) added as part of the Verilog-2005 standard.

SynaptiCAD has released version 15 of its family of Timing Diagram Editors and test bench generators. The major enhancement in the new version is the ability to create blocks of editable analog waveforms using simple Python-based equations.

SynaptiCAD has just released the first 64bit Linux version of VeriLogger Extreme, a Verilog simulation and debug environment. The 64bit simulator runs 30% faster than the 32bit version and can simulate much larger designs (64bit Linux applications can use a system's full memory, unlike 32bit applications which are limited to 3GB of memory).

For a limited time, SynaptiCAD will be giving away free “no strings attached” 6 month licenses for VeriLogger Extreme, a high-performance compiled-code Verilog 2001 simulator that significantly reduces simulation debug time. Free licenses will be available for both Linux and Windows versions of the simulator.

SynaptiCAD’s Gates-on-the-Fly (GOF), a Verilog netlist editor and incremental schematic viewer, has added schematic back annotation and waveform viewer cross-probing. Using one of SynaptiCAD's waveform viewers, you can view waveforms from a simulation (e.g. a VCD file) or a logic analyzer and show specific logic states annotated on GOF schematic windows. The schematic and the waveform displays are linked so that you can quickly control the simu...

SynaptiCAD announces the release of Gates-on-the-Fly (GOF), a Verilog netlist editor and incremental schematic viewer. GOF can edit very large netlists from a synthesis or layout tool that need changes to either meet timing closure specifications, fix functional logic bugs, or to repartition a design.

SynaptiCAD is proud to announce version 14 of their timing diagram editors: WaveFormer Pro, Timing Diagrammer Pro, and Data Sheet Pro. Dozens of new features have been added including support for Xilinx post-route timing files, sampled analog signals, and memory optimizations to handle waveform files with over 1 million signals. SynaptiCAD has also made improvements to its free waveform viewer.

SynaptiCAD is now the US and Canadian distributor for HDL Works EDA tools: Ease, HDL Companion, and IO Checker. These tools provide alternative graphical approaches for VHDL and Verilog code design which also complement SynaptiCAD's timing diagram editors and graphical simulation tools. EASE provides a state machine bubble editor, truth table designer, and block diagram design environment for generating VHDL and Verilog code. HDL Companion scans ...