SynaptiCAD's TestBencher Simplifies Random Transaction Generation

The new version of TestBencher eliminates many of the manual coding steps that were previously required to create a testbench that applies a set of weighted-random transactions with contrained-random input data to a model under test. A fully randomized testbench with uniform transactor weightings can now be created without manually writing a single line of HDL code, although the tool supports a mixed-approach of manual and automatically-generated testbench code.

TestBench Generation Methodology

The user graphically draws timing diagrams that represent the protocols for the testbench's transactions with time and state variables to indicate transaction input data. A transactor is generated for each timing diagram and these transactors can be triggered by function calls made by the user in a testbench transaction sequencer process. The user can then selectively insert these calls into the sequencer process using a dialog that lists all available transactor function calls along with buttons to control how the transaction is applied. Using this dialog, transactions can be applied sequentially or concurrently, transaction can be scheduled on a queue for later execution, and the input data to the transactions can either be directly specified (via hard-coded values or pulled from a data structure) or randomly generated.

After the user has finished generating his testbench, he can launch his HDL simulator from inside TestBencher using the contained BugHunter debugger to begin applying transactions to his design model. As each transactor executes, it captures the response from the design model and compares the response against an expected response. TestBencher supports both protocol checking and scoreboarding of transaction payloads using graphical constructs in the timing diagram to verify timing and payload data, with captured data values being stored in user-selected data structures (arrays, associative arrays, data files, etc).