The Verilog2VHDL tool now supports the following Verilog 2005 constructs: multi-dimensional arrays, signed regs and nets that convert to VHDL numeric_std.signed data types, Verilog 2005 event control expressions such as @(posedge foo, posedge bar), the new localparam keyword, module parameter port lists, and named parameter assignments.
The VHDL2Verilog tool also received several enhancements including better generation of bit ranges for parameters generated from VHDL constants and an option to translate VHDL integer literals into fixed-length bit strings for synthesized designs.
The V2V tools are stand-alone command-line programs, but SynaptiCAD’s graphical HDL debugger, BugHunter Pro, can also be used to configure options to the translators and launch them on files in an HDL design project. Using BugHunter in combination with the V2V tools, users can quickly translate a design, then compile and simulate both the original files and the translated files to compare their output, make any necessary corrections, then resimulate. The BugHunter debugger is compatible with the following VHDL and Verilog simulators: SynaptiCAD’s Verilogger Extreme, Cadence’s Incisive, Synopsys VCS, Mentor Graphic’s ModelSim, and Aldec’s ActiveHDL.
SynaptiCAD will also perform translation of HDL code as service, using their translators to do the bulk of the work, then making manual corrections as necessary. SynaptiCAD particularly recommends this service for designers who are not fluent in both Verilog and VHDL coding. The cost of the translation service typically depends on the size of the IP to be translated.
