SynaptiCAD presents IO Checker 2.2, the FPGA and PCB IO verification tool

IO Checker uses rules (based on regular expressions) to match the signals names in both the FPGA and PCB design environment. The rules can be generated automatically and be fine-tuned by the designer. This automated approach will often match 80% to 90% of all device pins.

SynaptiCAD-HDLWorks IO Checker Screen

The flexibility of IO Checker allows it to be used in any design flow and does not require any design methodology. The rules generator in combination with the sorted problem view allows engineers to validate a 1000+ pins device in about 30 minutes.

New functionality in IO Checker 2.2:

-Alternate device migration
-Improved power and ground checks
-Search widgets
-Xilinx Vivado pin reader
-New Device support:
-Altera: Cyclone V / Arria V / Stratix V
-Xilinx: Artix-7 / Kintex-7 / Virtex-7 / Zynq