GOF Overview
GOF graphically analyzes and edits large Verilog netlists that have been generated from a synthesis or layout tool. Netlists sometimes require changes to either meet timing closure specifications, fix functional logic bugs, or to repartition a design. Using GOF’s unique “incremental schematic” technology, you can easily find, view, and edit specific logic cones in your design on a schematic to visualize just the paths you need to see without unnecessary clutter.