SynaptiCAD's Timing Diagram Editors Simplify FPGA Synthesis

Using SynaptiCAD's methodology, the user firsts creates timing diagrams that define the interfaces between their design and external digital devices. These timing diagrams specify the required clock speeds for the design, delay times for signal data flowing into the design, and setup/hold requirements of external device inputs. From this information the timing diagram editors automatically generate one or more SDC files with appropriate SDC commands that can then be fed to the designer's preferred synthesis tool.

The timing diagram editors can also extract SDC timing constraints from timing waveforms created by simulations or captured from hardware with a logic analyzer.
In this methodology,
the user imports his simulation or logic waveforms into the timing diagram editor and annotates timing parameters between clock signals and IO ports to generate the SDC constraints. The timing constraint information comes from the relative distance between waveform edges instead of from IC data sheets in this case.

SynaptiCAD's tools support editing and updating of existing SDC files that were manually created. SDC commands can be “linked” in the tool, enabling users to create SDC files with a mix of manually written and automatically-generated SDC commands that update as changes are made to the timing diagrams or to linked SDC files. The tools also include built-in text editors with color-syntax highlighting for all SDC commands.