Lattice Semiconductor announced the immediate availability of Service Pack 1 for Version 8.0 of its ispLEVER FPGA design tool suite. Service Pack 1 is an important update for users of LatticeECP3™ FPGA devices.

Lattice Semiconductor announced that it has shipped over 200 million ispMACH 4000 complex programmable logic devices (CPLD). The Lattice ispMACH 4000 CPLD family provides a variety of design solutions, from glue logic and general purpose I/O expansion to voltage level translation and LED drivers. Engineers around the globe have widely adopted the ispMACH 4000 CPLD as a standard due to its balance of price, power and packaging options.

Lattice Semiconductor announced the formal opening of Lattice SG Pte. Ltd., its new Asia Operations Center. The opening was marked by a formal ribbon cutting ceremony and attended by Lattice executives Bruno Guilmart, President and CEO; Michael G. Potter, Chief Financial Officer; Clay Miller, Chief Information Officer; Byron Milstead, General Counsel; Douglas Hunter, Vice President of Corporate Marketing; and Willy Bowman, Vice President of Worl...

Lattice Semiconductor announced that eVision Systems GmbH will represent Lattice and its full range of products in the Central European video and surveillance market.

Lattice Semiconductor today announced that its LatticeECP3 FPGA family has been named Digital IC Product of the Year by Electronic Products magazine.

Lattice Semiconductor today announced the immediate availability of a $169 evaluation board for the ispClock 5400D programmable clock device. The new board is an easy-to-use platform for evaluating and designing with the ispClock5400D differential clock distribution device. The evaluation board can be used by itself to review the performance and in-system programmability of the 5400D device, or as a companion board and clock source for LatticeEC...

Lattice Semiconductor has announced that it has shipped over 25 million MachXO PLDs. Broadly adopted in a wide range of high volume, cost sensitive applications, customers worldwide are using the MachXO PLD family due to its unparalleled ease-of-use, flexibility, system integration and price.

Lattice Semiconductor and Praesum Communications today announced the availability of the Serial RapidIO 2.1 endpoint soft IP core for the LatticeECP3 FPGA family. The core supports 1x, 2x and 4x lane configurations at up to 3.125Gbps lane speeds, offering the lowest cost, lowest power programmable SRIO solution in the industry. Lattice also announced that it has licensed this IP core from Praesum and has full rights to use and sub-license the Ser...

Lattice Semiconductor has announced that Broadband Technology AB will represent Lattice and its full range of products in the Nordic market, including Denmark, Finland, Norway and Sweden.

Lattice Semiconductor today announced that Allyanz Pty Ltd will represent Lattice and its full range of products in Australia and New Zealand.

Lattice Semiconductor today announced that the LatticeECP3-150 FPGA, the highest-density device in its award-winning high-value, low-power ECP3 mid-range FPGA family, has been fully qualified and released to volume production.

Lattice Semiconductor today announced that its mid-range, low power LatticeECP3 FPGA family has won the highly regarded e-Legacy Awards competition sponsored by Electronic Product Design magazine. Lattice was honored in the coveted Environmental Design category, and was the only programmable logic company to be named a finalist in any of the competition's award categories.

Lattice Semiconductor has announced that Redtree Solutions Ltd will represent Lattice and its full range of products in France, Benelux, the UK and Ireland.

Lattice Semiconductor today announced it will collaborate with Beyond Semiconductor in the development of compiler tools for Lattice's soft processors. The collaboration will include updates and performance improvements for Lattice's embedded processor IP compilers and development tools.

Lattice Semiconductor has announced Version 8.0 of its ispLEVER FPGA design tool suite, which includes many enhancements for the design of high speed double data rate (DDR) interfaces for the LatticeECP3 FPGA family. These enhancements include automatic interface code generation to increase design productivity and reduce coding errors, as well as enhanced timing analysis that provides more transparency to circuit timing details.

Lattice Semiconductor today announced the addition of two new higher performance devices to its second generation Power Manager II product family. Both the ispPAC-POWR1014-2 and ispPAC-POWR1014A-2 devices integrate higher voltage charge pumps with programmable current to control MOSFETs in Hot Swap and Sequencing applications.

Lattice Semiconductor Corporation has announced Version 5.2 of its PAC-Designer mixed signal design tool suite with new device support and productivity features. The PAC-Designer 5.2 software now supports two new higher performance Power Manager II products: the ispPAC®-POWR1014-2 and ispPAC-POWR1014A-2 devices. The POWR1014/A-2 devices are ideal for integrating Hot Swap control, voltage rail supervision and power supply sequencing ICs. PAC-Desi...

Lattice Semiconductor Corporation and Affarii Technologies Limited, a solutions provider for networking and telecommunications applications, today announced that they have developed a complete 3G/4G-based Remote Radio Head (RRH) solution for wireless infrastructure customers. This is the first time a full RRH solution has been made available using low power, low cost FPGAs that allows low power RRHs to be deployed without sacrificing flexibility ...

Lattice Semiconductor has announced the immediate availability of the new MachXO Control Development Kit as well as 12 new reference designs, ideal for prototyping system control functions such as temperature and current monitoring, power supply sequencing, fan control and fault logging, that are commonly found in telecom infrastructure, server, industrial and medical applications. The new kit offers designers of CPLDs and low-density FPGAs a com...

Lattice Semiconductor and Epson Toyocom Corporation today announced a low-cost reference clock solution for SERDES applications. By utilizing Lattice's ispClock 5400D device and the appropriate SG-710ECK CMOS oscillator from Epson Toyocom, a designer now has a low cost reference clock for SERDES applications such as XAUI or SDI Video. With this solution, SERDES-based designs no longer will require an expensive LVDS or LVPECL high frequency oscill...