Analysis

Lattice FPGA Family Wins e-Legacy Awards

17th November 2009
ES Admin
0
Lattice Semiconductor today announced that its mid-range, low power LatticeECP3 FPGA family has won the highly regarded e-Legacy Awards competition sponsored by Electronic Product Design magazine. Lattice was honored in the coveted Environmental Design category, and was the only programmable logic company to be named a finalist in any of the competition's award categories.
While power saving is a key driver for electronics designers, the judges were impressed that the LatticeECP3 FPGA could also deliver upfront cost-savings, said Tim Fryer, managing editor of Electronic Product Design magazine. In some cases, the ECP3 device's environmental benefit might be secondary to low cost, while in the majority of projects the ECP3 device's low power would be a prime consideration.

The Environmental Design award recognizes an electronic design that is environmentally sensitive due to its energy saving and power efficiency. Finalists were chosen by a panel of industry experts, and the winners were selected by the readers of Electronic Product Design magazine. It is the combination of expert judges and the public vote that gives the e-Legacy Awards their credence, so both finalists and eventual winners have much to be proud of, said Fryer. Winners were announced at the e-Legacy Awards luncheon at the Roof Gardens in Kensington, London on Wednesday, November 4th.

We are honored to receive this award for our ECP3 FPGA family, said Sean Riley, Lattice Corporate Vice President and General Manager of High Density Solutions. Low power is a priority for systems with tight operating budgets as well as an environmental responsibility for the companies that deploy them. It seems almost daily that new and conflicting claims and counterclaims are made for low power FPGAs, and so it is very gratifying that our ECP3 FPGA family has been recognized for its low power by independent judges and voters. Power definitely does matter, and our ECP3 FPGA family was designed from the bottom up to be the lowest power SERDES-capable device in the industry, without sacrificing the benefits of high speed serial I/O and processing capabilities.

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