Lattice Releases Development Platform for SERDES and Video Clock Distribution

Typically, expensive oscillators with LVDS or LVPECL interfaces are used as a reference clock for FPGA SERDES interface applications. The ispClock5400D device provides ultra low-jitter differential clock outputs that can be used to drive both the general purpose clocks and the SERDES reference clocks for FPGAs, ASSPs and ASICs. The evaluation board demonstrates how to interface a low-cost CMOS interface oscillator to the ispClock5400D device to produce high quality clocks for XAUI applications or 270 MHz SDI video applications.

This new evaluation board provides an excellent development platform for differential clock implementations with the ispClock5400D device. The platform provides a way to interface rapidly to bench test equipment to confirm the low period and phase jitter performance of the 5400D family, said Shyam Chandra, Lattice's Product Manager for Mixed Signal Devices. Traditional clock distribution ICs do not help with timing challenges in a circuit board; in fact, in many cases fixing timing problems requires new circuit board layout and fabrication. Our new evaluation board showcases the skew control flexibility of the ispClock5400D device, which costs far less than traditional clock distribution ICs.