Xilinx and Inova Semiconductors Simplify Design Integration of High-Bandwidth Video Connections for Automotive Applications
At Embedded World 2010, Xilinx and Inova Semiconductors introduced an Automotive Pixel Link (APIX(R)) IP solution for the Xilinx(R) Automotive (XA) family of low-cost Spartan(R)-6 field programmable gate arrays (FPGAs). The configurable core supports multiple high-bandwidth video and communications links in a single device to transfer high-quality, real-time video from two or more cameras or processing units to in-vehicle displays. This highly integrated connectivity solution is targeted at infotainment and driver assistance applications.APIX is the latest Gigabit/s Pixel Link interface from Xilinx Alliance partner Inova Semiconductors, providing point-to-point connectivity designed for minimal electro-magnetic interference (EMI) and maximum transmission distances. With the APIX IP core now available for Xilinx's newest line of XA Spartan-6 FPGAs (also announced separately today), automotive developers can integrate multiple transmit and receive APIX links with minimal engineering overhead. In addition to high-bandwidth video, the APIX link allows for full duplex communication and power can be transmitted over just one cable to further streamline connectivity.
The need to transport real-time, high resolution digital video from various media or camera sources to displays throughout the vehicle is a growing concern for automotive developers, said Nick Difiore, director of automotive systems architecture and platforms at Xilinx. Both the APIX core and XA-Spartan-6 FPGAs are designed for high-speed connectivity. Bringing them together enables a highly integrated and scalable multi-transceiver architecture that delivers the video bandwidth and increasing number of connections needed, while also reducing overall system cost. With the addition of the APIX core to the comprehensive portfolio of interface options offered by Xilinx and our Alliance network, developers now have even more choice and greater design flexibility.
The APIX IP Core
The APIX core is a software configurable IP block that can be adapted to application-specific bandwidth, video interface, and control signal requirements with adjustable driver characteristics, selectable operating modes, and spread spectrum-clocking capabilities. The APIX IP utilizes the multi-gigabit transceiver (MGT) hard blocks of the XA Spartan-6 FPGA to maximize performance and integration while reducing system cost. It is fully compatible with the standalone APIX INAP125T24 (transmitter) or INAP125R24 (receiver) devices, including the ASHELL automotive-specific communication protocol for secure data transmission over the full duplex sideband interface. The ASHELL option can be switched off, if not required.
Developed in collaboration with leading car makers and automotive electronic suppliers, our licensable APIX technology offers a solid, ruggedized connectivity standard that is qualified by eight out of ten major automotive OEMs worldwide and used today by numerous other semiconductor providers, said Thomas Rothhaupt, director of sales and marketing at Inova Semiconductors. By providing our production-proven interface technology for XA Spartan-6 FPGAs, we are adding to our APIX silicon ecosystem with the ability to utilize built-in FPGA MGTs for advanced systems with cameras and displays, such as head units or cluster displays with camera inputs.
Enabling Next-Generation Applications
Many next-generation driver assistance and infotainment systems have multiple video sources and sinks. For infotainment head units, in which FPGAs are already used in a companion chip role, the APIX IP core takes advantage of the high-speed serial transceivers embedded in the XA Spartan-6 FPGA and provides an additional level of integration that saves valuable board space and reduces component count. Other applications include vehicle surround view systems, where multiple APIX cores on the XA Spartan 6-FPGA enable a single-chip solution that aggregates four or more high-bandwidth camera inputs and eliminates the need for multiple external serializer/deserializer (SerDes) devices. A similar integration/cost benefit is also realized in rear seat entertainment systems, where multiple video display modules must be sourced from a single audio/video distribution unit.
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