The Threat Of Instability

15th May 2013
Posted By : ES Admin
The Threat Of Instability
Addressing one of the most difficult reliability challenges facing the semiconductor manufacturing community today. By Christopher L. Henderson, President of Semitracks Inc,. This ES Design magazine article is based on a white paper, with editorial contributions by Peter J. Hulbert and David W. Rose of Keithley Instruments.
Bias temperature instability (BTI), particularly negative BTI (NBTI) in p-channel transistors, affects small feature size devices and is quite difficult to reduce or eliminate. As feature sizes become smaller, the effects of NBTI become more pronounced, resulting in increases in threshold voltage and decreases in drain current and transconductance in p-channel devices. NBTI results from a positive charge buildup in p-channel transistors. It occurs at low negative gate-to-source voltages and does not result in an increase in gate leakage current. Rather, it affects off-state drain-to-source leakage and reduces the drive current. Generally, this problem is worse than standard hot carrier degradation because it results in permanent interface traps being generated, reducing device lifetime.

Most of these NBTI phenomena have implications for measurement methodologies. For example, there are frequency dependencies that must be considered in choosing measurement techniques. Today, it is widely recognised that most measurements must make use of ultra-fast pulse technology. If one does not use this approach, NBTI effects can be completely missed under DC-only test conditions, and resulting predicted DC lifetimes may be much shorter.

NBTI typically increases with decreasing channel length. This is due to the increased contribution from the source and drain overlap regions. It can be quite pronounced in deep sub-micron technologies. At 90nm channel lengths, the change in threshold voltage can exceed 100mV and the change in drive current can approach 10%. As a result, NBTI is now considered to be one of the most difficult reliability challenges facing the semiconductor manufacturing community today.

Physics Of P-Channel FETs

For NBTI, interface traps are amphoteric, meaning they can be either donors or receptors depending on their energy state. If the trap is below the midgap or the intrinsic Fermi level, then it is positively charged when it is empty. Above midgap, traps are acceptors, or negatively charged when full. In an inverter PMOS transistor, there are donors below midgap, but above the Fermi, that are positively charged. This answers the questions of where the positive charge is coming from and why NBTI is worse for p-channel FETs. The implications are that p-channel transistors suffer from two problems: not only are donor traps positively charged, but they also add to any positive fixed charge that might be present.

Without going into all the details of recent research, it should be noted that the working kinetic model of NBTI is built around a reaction-diffusion process, which is described by the equations and diagram in Figure 1. SiH is prevalent in the model, and a hole catalyses the reaction, producing a positive silicon ion and free hydrogen. The model equations can be used to calculate forward and reverse reaction rates, and solve the diffusion portion of the model. Many people believe that the electric field dependency must be due to the kinetics of the reaction phase. The field across the holes must reduce the amount of energy necessary to catalyse the reaction, allowing it to occur more quickly. This implies a thermo-chemical process.


Figure 1: Reaction-diffusion model of NBTI


With regard to damage recovery, it can occur under pulsed conditions when tests are conducted at low frequencies. It has been shown that lower threshold voltage shifts and on-current shifts occur at higher frequencies. However, the measurements were made with slow measurement techniques. Under these test conditions, NBTI damage occurs when the input pulse (VG) to the device is low and the output pulse (VD) is high. The channel hot carrier damage region occurs when VG is high and VD is high, so there is an overlap. Some work has been published that shows how channel hot carriers can actually enhance the NBTI reaction.

Reliability Modelling

The current state of the NBTI models is limited by the knowledge on the physics of this mechanism. However, engineers have standardised on a basic set of models for reliability calculations; the JEP-122 model.

Reliability modelling like this has led to research that reveals the relationship between NBTI and process variables, such as nitridation, annealing, and burn-in practices. For example, NBTI is worse with oxynitride films, which are used to reduce boron penetration. The nitrogen facilitates bulk/interface trap generation. Furthermore, because NBTI is affected by temperature, it is exacerbated during burn-in and its effects are difficult to separate from standard hot carrier damage.

Researchers have found that the appropriate annealing process can reduce these problems. Specifically, deuterium annealing can make an oxide much less susceptible to both hot carrier and NBTI damage. As an energetic electron strikes the hydrogen at the interface, it can displace the hydrogen atom, causing a trap. The bond energy between the hydrogen and the silicon is relatively low, making it relatively easy for the hot electron to displace the hydrogen. The extra electron in the deuterium creates a stronger bond between the deuterium and the silicon, making the deuterium more difficult to displace. This results in fewer traps, less damage to the transistor, and greater reliability.

Ultra-Fast BTI Measurement

In BTI characterisation, the instrument functionality required for process reliability measurements is different from that needed in modelling measurements. As might be expected, these differing requirements have implications for both instrumentation hardware and software.

Typically, process reliability monitoring is intended to provide insight into process trends related to stress induced shifts in device operating parameters. The measurements taken are not intended to provide insight into device physics. Therefore, device test structures are designed to highlight specific mechanisms related to production processes. This means that measurement techniques and methodologies must highlight relative stress induced parametric shifts over time and process batches.

An example of instrumentation that pushed the limits of process reliability monitoring in the past is Keithley’s large scale SMU-per-pin measurement configurations. These systems were developed for process integration and production operations where the goal is to fit reliability data to an existing model. Such systems can be used to refine statistical models but offer little visibility into physical mechanisms that underlie the models.

Today, most production BTI testing is performed with fast DC SMUs, but this is not adequate for reliability modelling applications. DIR or ‘designed-in reliability’ has become a standard practice in today’s fab. BTI effects have made this effort more challenging. Not only is the fundamental measurement difficult with traditional tools, but large statistical samples are required to overcome the noise of the extrinsic thin film defects.

To meet these requirements, Keithley has integrated ultra-fast I-V measurement capabilities into a purpose-built test environment, making even complex test sequences easy to set up and automate with semi-automatic and fully automatic probe stations. The instrument hardware supports a wide range of pulse waveforms with synchronised measurements, as alluded to in Figure 2. In this basic test setup, the source and well are grounded, while the gate and drain are both connected to pulse or waveform generators that have integrated voltage and current measurement capability. This seemingly simple configuration offers all the capability needed for BTI testing; however, a number of practical challenges must be overcome.


Figure 2: Basic BTI test setup and possible waveforms


One key issue is that, rather than a simple two-level pulse, the instrumentation needs to support a wide range of pulse shapes with synchronised measurements. Although easily stated, this is a major undertaking for the instrument designer.

Besides the right hardware configuration, capabilities, and interconnects, BTI-centric software capabilities are also required. At Keithley, system design started with the advanced wafer- and cassette-level automation capabilities of the Automated Characterisation Suite (ACS) and then added dedicated GUIs for advanced ultra-fast BTI measurements. A key feature is the GUI’s ability to harness the full precision timing capability of the waveform generator, along with its synchronised measurement capability — without adding complexity to the set-up process.

This feature is very important in reliability testing, where flexible and precise control of the stress/measure timing sequence is needed for valid measurements over a range of conditions. The ultra-fast BTI GUI provides a choice of linear, log, or customer ‘list’ stress sequences. The first measurement can be triggered in as little as one microsecond after stress begins. This is done with 5ns timing accuracy, so even the earliest stages of degradation can be accurately studied. Moreover, the user has control over test variables such as first stress time, last stress time, and stress/measure cycles per decade.

In addition to the spot measurement and sweeps shown in Figure 2, the Keithley BTI GUI allows up to 20 waveform building blocks to be strung together to form a test sequence that is executed at each stress/measure timing interval. The user can also set up sample measurements, and string together a variety of measurement waveforms.


Figure 3: Example of a BTI measurement sequence


Different stress and measurement intervals and waveforms are completely under user control. Notice the triangular sweep areas in Figure 3 that are used to characterise VTH between each stress interval. The triangle indicated by the red arrow is made up of the two building blocks shown in the set-up GUI below the waveform diagram, i.e., the rising sweep and the descending sweep. The rising sweep, labeled SweepUP in the GUI display, measures 10 points from 0 to 1.0V, along with drain current measurements. The same measurements are made during SweepDOWN. During execution, the system timing is used to set the speed of the measurement steps in these smooth sweeps. In this case, 100ns per step was chosen.

The Model 4225-RPM expands on the Model 4225-PMU's capabilities by providing four additional low current ranges for current sensitivity down to tens of pico Amps, which is generally required for BTI measurements. Keithley’s triax Multi-Measurement Performance Cables (MMPCs) that have characteristics permitting their use with all the Model 4200-SCS measurement capabilities, i.e., ultra-fast I-V, DC I-V, and C-V. These are the blue cables in the upper left photo of Figure 4 connecting the 4225-RPM modules to the probe heads. Note that these are kept short so the pulse source is as close as possible to the probe pins.


Figure 4: Complete solution for ultra-fast BTI characterisation


A block diagram of the system is shown in Figure 5. The system’s dedicated BTI GUI includes wafer mapping capabilities that makes it easy to select the test structures or actual devices to be measured. (See wafer map in Figure 4.) By default, the GUI provides degradation measurements. However, when needed, the GUI also provides a setup for recovery measurements. Recovery/measure timing is set up much like the stress/measure timing and includes AC or DC recovery conditions as well.

Researchers agree on several aspects of NBTI. NBTI is a hole catalysed reaction that has a pronounced effect on p-channel transistors, and is quite difficult to reduce or eliminate, particularly in devices with short channel lengths. NBTI field dependence is due to the reaction phase, not a field drift component. The damage increases the threshold voltage shift. Interface traps are certainly involved, but there may be another component such as fixed charge as well.


Figure 5: Block diagram of the Keithley BTI characterisation system, showing MMPC cabling from the 4225-RPM to the device under test (DUT)


Ultra-fast measurement techniques must be used to characterise NBTI and obtain the correct degradation slopes. The measurements need to be made in less than 50μs to be valid. The damage appears to be related to the transport of hydrogen through the oxide. Nitrogen decreases the activation energy of the process. Damage recovery under pulsed operation can increase the lifetimes of transistors by a factor of 4 to 8, or even larger under certain conditions. Finally, there is some debate as to whether the damage is caused by interface traps or bulk oxide traps.

Keithley has developed a version of its Model 4200-SCS semiconductor characterisation system with ultra-fast BTI measurement capabilities that include both degradation and recovery characterisation. Its software GUI makes it easy to set up and control all aspects of BTI testing for both research modelling and production reliability measurements.

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