Renesas Technology to develop new CPU architecture for microcontrollers

The new architecture will have innovative advances over the M16C and H8S 16-bit CPUs and R32C and H8SX 32-bit CPUs that Renesas Technology currently offers, while offering compatibility with the existing families in terms of CPU instruction sets, peripheral register sets and development tools. It will combine the excellent code efficiency of the M16C and R32C CPUs with the high-speed data processing of the H8S and H8SX CPUs. Moreover, the new CPU architecture will further extend the low power consumption and low noise characteristics of both family lines. With these capabilities, Renesas aims to achieve the world’s best overall performance considering code efficiency, processing performance (MIPS/MHz), power consumption and cost competitiveness. Code efficiency is especially important since it helps to minimize system program size and reduce overall system cost by allowing the use of less flash memory.

By employing this new architecture, Renesas aims to reduce code size by 30% and CPU power dissipation by 50%.

“Renesas’ broad MCU product offerings have been successful in the embedded market for many years, backed by powerful product development, field-proven manufacturing capabilities and a rich system-development environment,” said Hideharu Takebe, board director and general manager, MCU business group, Renesas Technology Corp. “Renesas’ MCUs have won over 10,000 designs annually, gaining accelerated acceptance in applications such as consumer products, automotive systems, industrial products, office equipment, and communication products. As a next step, we are developing next-generation CPUs for 16- and 32-bit markets under a single architecture, in response to the growing demand for both 16- and 32-bit MCU products. With this announcement, our present and future customers can be assured that Renesas is committed not only to supporting our existing MCU product families, but also to providing a solid upgrade path. Renesas continues to lead the MCU market by building on its global leadership. (No. 1 share*2 worldwide)”
The project to develop the next-generation 16- and 32-bit CISC*3 CPUs is underway as Renesas celebrates the fourth anniversary of its establishment. The company plans to dedicate substantial resources to the project, and the new CPUs are expected to further expand Renesas’ MCU business.

Devices incorporating CPUs based on the new architecture will scale from 16-bit to 32-bit CISC performance. They will be very easy to use and will shorten development times for system manufacturers. Moreover, by maintaining compatibility with existing products, the new CPUs will allow existing and future customers to preserve their engineering investments.

Renesas’ standard development environment, the High-performance Embedded Workshop, will also provide total support for the new CPUs as well as its existing MCUs. This will simplify the migration of software resources from the existing products to MCUs based on the new CPUs, and accelerate the development and debugging of new software. To ensure that customers will have access to a wide selection of development tools, Renesas will continue to work with third-party companies and actively share information concerning the new architecture via the Web under Renesas’ Alliance Partner Program.

The company will continue to develop new products and provide support for customers using currently available MCU products. The specifications of the new CPUs will be released in early 2008 and the first devices with the new CPUs are expected to become available during Q2, CY2009 based on Renesas’ 90nm flash MCU process. Devices for automotive applications are expected to be introduced after those for non-automotive applications, with the schedule determined by market requirements.