Memory manufacturer, Intelligent Memory, has released DRAMs in traditional SDRAM-technology with on-chip ECC functionalities. As IM started off their ECC DRAM series with DDR1, DDR2, DDR3 and LPDDR technologies originally, now coming up with SDRAM-devices sounds like a technological step backward.
"After Micron announced the End-Of-Life of their 512 Megabit SDRAM devices and in parallel new demands were coming up for SDRAM components in x32 configurations, we wanted to fill this gap with our highly reliable ECC DRAMs. And customers do not only get an unbeatable quality and longevity with our ECC SDRAMs, but also the prices are very competitive!", explained Joseph Chan, General Manager of Intelligent Memory.
IM's new ECC SDRAM components come in capacities of 256 and 512Mb with the 256Mb versions being offered as 'XR' ECC DRAMs with extra robustness by cell-twinning. All ECC SDRAM devices are available in a common bit-width of x8 or x16 in a standard TSOP 54 pin package, but are also available in the space-saving x32 configuration which is packaged either in TSOP 86 pin or BGA 90 ball housing, especially for applications having limited board-space. As standard, all ECC DRAM components allow to be operated at industrial temperatures of -40 to 85°C, but due to their high reliability are also available for temperature-ranges as high as 125°C, which is rare in the DRAM industry.
Why DRAM with ECC?
Transient single-bit-errors of DRAM memory are responsible for the majority of randomly appearing malfunctions of any electronics application, no matter if we talk about the home-computer showing a blue screen, the car navigation system re-booting or showing strange stripes on the screen or other effects and fails. A re-boot always brings the application back to work and the malfunction can not be repeated nor proven.
DRAM-memory is sensitive to heat, radiation or ageing. It even shows random errors under intensive use or by the recently discovered row-hammering phenomenon and it has numerous further little glitches caused by the nature of DRAM-technology itself.
The result are random fails at any time during operation of an application. However, the vast majority of these DRAM-issues only cause a single memory-cell in the DRAM chip to change one databit from 0 to 1 or vice versa. Such bit-flips are mostly transient and disappear after overwriting the bit. Furthermore, not all bit-errors hit into critical data or program code in the memory, but still they sometimes cause system malfunctions or crashes. In many cases data gets corrupted without being noticed for some time until the data can no longer be recovered.
Wouldn't it be better to be able to avoid such hiccups? Especially safety-critical applications for automotive, space, avionic or medical industries, but also networking devices, storage systems, access controls or smart metering products require to be always available without any downtimes or risk of data-corruption.
For many years ECC error-correction technology has been used successfully in server-systems, assuring these to run 24/7. Unlike desktop PCs or laptops, servers never need to be re-booted due to erratic behavior or crashes, although they typically run the same operating system. A major part of that stability and availability is provided by the fact that servers utilise processors having ECC error-correction functionalities which can verify and correct databit-flips in the DRAM memory.
IM has transferred this error correcting logic right into their DRAM memory chips, while keeping them fully compatible to all JEDEC standard specifications. As a result, any application that uses DRAM memory in DDR1, DDR2, DDR3 or LPDDR - and now also legacy SDRAM - technology can be lifted up to a server-like reliability-level by simply using Intelligent Memory's ECC DRAM components instead of conventional DRAMs. No software and no hardware modifications are required.
For people who can't get enough reliability, Intelligent Memory produces the 256Mb capacities of their ECC DRAM devices optionally with 'eXtra Robustness', named XR ECC DRAM. These devices use two cells per databit to achieve long data-retention times and robustness against radiation or heat.