Synopsys Inc

Address:
700 East Middlefield Road
Mountain View

CA 94043
United States of America

Phone: 001 650 584-5000

Web: www.synopsys.com


Synopsys Inc articles

Displaying 1 - 20 of 629

Synopsys completes acquisition of QTronic

Synopsys completes acquisition of QTronic
Synopsys has announced it has completed its acquisition of QTronic. The rapid growth of software used in vehicles, combined with the complex interaction of hardware, creates an enormous challenge for automobile manufacturers and their suppliers developing future powertrain, advanced driver assistance, electric vehicles, and autonomous driving systems. 
22nd October 2019

IC Compiler II for next-gen communications network design

IC Compiler II for next-gen communications network design
Synopsys has announced immediate availability of the latest release of its flagship IC Compiler II place-and-route system that includes several new innovative technologies to deliver Quality-of-Results (QoR) and fastest Time-To-Results (TTR) for the next wave of designs across a wide range of vertical markets, including automotive, cloud computing, AI, networking and wireless applications.
15th July 2019

Duo enable Astera Labs to develop PCIe 5.0 Retimer SoC

Duo enable Astera Labs to develop PCIe 5.0 Retimer SoC
Synopsys has announced that Astera Labs successfully utilised Synopsys' Fusion Design Platform, Verification Continuum Platform, and Design Services to develop its breakthrough connectivity technology for next-gen servers, all running on AWS. The collaboration represents two industry milestones: the first large-scale design fully implemented and verified from start to finish on a third-party public cloud, and the first PCIe 5.0 retimer for heterogenous compute and workload-optimised servers.
31st May 2019


Inference software library for power-efficient neural networks

Inference software library for power-efficient neural networks
The availability of the new embARC Machine Learning Inference software library has been announced by Synopsys to facilitate development of power-efficient neural network system-on-chip (SoC) designs incorporating Synopsys' DesignWare ARC EM and HS DSP Processor IP. 
2nd April 2019

Design platform enables tapeout of gate-all-around transistor SoC

Design platform enables tapeout of gate-all-around transistor SoC
It has been announced by Synopsys, that Synopsys' Fusion Design Platform, including the IC Compiler II place-and-route system, has enabled the successful tapeout of Samsung Foundry's industry-first gate-all-around (GAA) system-on-chip (SoC) test chip comprising several high-performance, multi-core subsystems. 
12th March 2019

Accelerating software development for IoT applications

Accelerating software development for IoT applications
Provider of high-quality, silicon-proven IP solutions, Synopsys, has announced the new DesignWare ARC EM Software Development Platform to accelerate software development and debug of ARC EM processor-based system-on-chips (SoC) for a wide range of ultra-low power embedded applications such as IoT, sensor fusion, and voice applications. 
28th January 2019

Silicon-proven DesignWare IP for PCI Express 4.0

Silicon-proven DesignWare IP for PCI Express 4.0
It has been announced by Synopsys that Habana Labs has achieved first-pass silicon success for its Goya inference processor system-on-chip (SoC) using DesignWare Controller and PHY IP Solutions for PCI Express 4.0. The silicon-proven IP, operating at 16 GT/s data rate and supporting all key features of the PCI Express 4.0 specification, and compliant with PCI Express 3.0, enabled Habana Labs to meet the required real-time data connectivity of their AI SoC. 
22nd January 2019

Extending capabilities of enterprise application security testing

Extending capabilities of enterprise application security testing
The availability of a new version of Synopsys’ Coverity static application security testing (SAST) solution, which enables organisations to build secure applications faster, has been announced. The latest release of Coverity addresses three increasingly important needs for enterprise application security teams: scalability, broad language and framework support, and comprehensive vulnerability analysis. 
16th January 2019

IC Validator verifies 12.8Tbps network switch

IC Validator verifies 12.8Tbps network switch
It has been announced by Synopsys, that Innovium has adopted the Synopsys IC Validator tool for physical signoff. Innovium deployed IC Validator on their flagship 12.8Tbps throughput TERALYNX switch. To meet their aggressive time-to-market schedule, Innovium used IC Validator across more than 250 CPU cores to take advantage of IC Validator's performance scaling.
10th January 2019

Updates advance optical design for AR/VR systems

Updates advance optical design for AR/VR systems
The release of version 2018.12 of the Synopsys RSoft Photonic Component Design Suite, which introduces new features to advance the design of optics used in augmented reality and virtual reality (AR/VR) systems, has been announced by Synopsys. The latest RSoft release supports Synopsys' optical design workflow for nano-textured diffractive optical elements that enable smaller, lightweight AR/VR devices with improved displays and immersive experiences.
2nd January 2019

Accelerate InP-based PIC design and production

Accelerate InP-based PIC design and production
It has been announced by Synopsys that, in conjunction with the American Institute for Manufacturing Integrated Photonics (AIM Photonics), Infinera's process design kit (PDK) is now available for Synopsys' OptSim Circuit tool. The addition of the Infinera PDK to OptSim Circuit enables users to schematically capture, simulate, and verify indium phosphide (InP)-based photonic integrated circuit (PIC) designs with Infinera's PDK building blocks.
10th December 2018

Memory test and repair solution enhanced for embedded MRAM

Memory test and repair solution enhanced for embedded MRAM
  It has been announced by Synopsys, that the DesignWare STAR Memory System solution now offers new memory built-in self-test (BIST), repair, and diagnostic capabilities for embedded MRAM (eMRAM)-based designs, with initial support for GLOBALFOUNDRIES (GF) eMRAM on the 22FDX process. 
2nd November 2018

Synopsys and SMART Photonics Expand InP-Based PIC Design Automation

Synopsys and SMART Photonics announce a new, production-ready process design kit based on SMART Photonics' Indium Phosphide process is now available in Synopsys' OptSim Circuit tool to support InP-based photonic integrated circuit design and simulation. Synopsys' PIC Design Suite, which comprises OptSim Circuit and OptoDesigner tools, provides a seamless PIC design flow from idea to manufacturing from a single solutions provider. The addition of the SMART PDK to OptSim Circuit, combined with the PDK's availability in OptoDesigner, enables users to use the PIC Design Suite to schematically capture and simulate InP-based PIC designs with the SMART PDK building blocks, and then synthesize and verify a SMART-foundry-compatible layout.
22nd October 2018

Expertise in emulation being brought to bear

Expertise in emulation being brought to bear
It has been announced that Synopsys was selected by the Defense Advanced Research Projects Agency (DARPA) for the Posh Open Source Hardware (POSH) program to create new innovation in analog mixed signal verification as part of its Electronics Resurgence Initiative (ERI), in partnership with Lockheed Martin and Analog Devices, using Synopsys’ ZeBu emulation technology. 
19th October 2018

Optimised solutions for Arm-based designs showcased

Optimised solutions for Arm-based designs showcased
At Arm TechCon, at the San Jose Convention Center in San Jose, California, October 16th to 18th, Synopsys, will showcase its Synopsys Design Platform, Verification Continuum Platform, and DesignWare IP. Synopsys offers optimised solutions and professional services to accelerate innovation throughout the Arm-based product design flow. 
10th October 2018

Collaboration delivers design flow for packaging technologies

Collaboration delivers design flow for packaging technologies
It has been announced by Synopsys, that the Synopsys Design Platform fully supports TSMC's wafer-on-wafer (WoW) direct stacking and chip-on-wafer-on-substrate (CoWoS) advanced packaging technologies. The design platform enablement is combined with the 3D-IC reference flow.
5th October 2018

Partner Awards bestowed at the Open Innovation Platform Forum

Partner Awards bestowed at the Open Innovation Platform Forum
Four ‘2018 Partner of the Year’ awards have been bestowed by TSMC upon Synopsys for Interface IP and joint development of five nanometre (nm) design infrastructure and Virtual Design Environment (VDE) Cloud Solution, plus joint delivery of the Wafer-on-Wafer (WoW) Design Solution. 
4th October 2018

Automotive-grade IP in seven nanometre process for ADAS designs

Automotive-grade IP in seven nanometre process for ADAS designs
The delivery of automotive-grade DesignWare Controller and PHY IP for TSMC's seven nanometer (nm) FinFET process has been announced by Synopsys. The DesignWare LPDDR4x, MIPI CSI-2 and D-PHY, PCI Express 4.0, and security IP implement advanced automotive design rules for TSMC seven nanometre process to meet the stringent reliability and operation requirements of ADAS and autonomous driving system-on-chips (SoCs).
3rd October 2018

Production-ready flow for advanced customer designs

Production-ready flow for advanced customer designs
It has been announced that TSMC has certified the Synopsys Digital and Custom Design Platforms for the latest version of its most advanced, extreme-ultra-violate (EUV)-based, five nanometer (nm) process technology. This certification is the result of an extensive, multi-year collaboration to deliver an optimised design solution that speeds the path to next-generation designs. 
2nd October 2018

Accelerating 3nm process development with DTCO innovations

Accelerating 3nm process development with DTCO innovations
Synopsys has announced a collaboration with IBM to apply design technology co-optimisation (DTCO) to the pathfinding of new semiconductor process technologies for the 3nm process node and beyond. DTCO is a methodology for efficiently evaluating and down-selecting new transistor architectures, materials and other process technology innovations using design metrics, starting with an early pathfinding phase before wafers become available.
16th August 2018


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