Synopsys Inc Articles
Collaboration reference methodology for compute designs
Synopsys has announced its collaboration with Samsung Foundry to deliver a new certified digital implementation, timing and physical signoff reference flow accelerating high-performance compute designs using the Synopsys Fusion Design Platform.
CXL 2.0 Verification IP solution for SoC performance
Synopsys has announced the availability of the Verification IP (VIP) for Compute Express Link (CXL) 2.0 designed for performance in data-intensive system-on-chips (SoCs).
Reference flow for ASIL D-compliant SoC design
Synopsys and Samsung Foundry has announced the release of a validated automotive reference flow to streamline SoC hardware design for in-system test, implementation, verification, timing and physical signoff for ISO 26262 compliance. This reference flow is targeted for automotive safety integrity level (ASIL) D autonomous driving and advanced driver-assistance systems (ADAS) applications.
Brining machine learning inference to the embedded edge
Synopsys has announced its collaboration with SiMa.ai to bring its machine learning inference at scale to the embedded edge. Through this engagement, SiMa.ai has adopted key products from Synopsys DesignWare IP, Verification Continuum Platform, and Fusion Design Platform for the development of their MLSoC, a purpose-built machine-learning platform targeted at specialised computer vision applications, such as autonomous driving, surveillance, and ...
3DIC Compiler solution for high-bandwidth memories
Synopsys has announced that its 3DIC Compiler solution enabled Samsung Foundry to design, implement and tape out a complex 5-nanometer SoC featuring eight high-bandwidth memories (HBMs) in a single package.
PCI Express 5.0 IP interoperability with xeon scalable processor
Synopsys has announced its collaboration with Intel to achieve successful system-level interoperability between the Synopsys DesignWare Controller and PHY IP for PCI Express 5.0 and future Intel Xeon Scalable processors (codename Sapphire Rapids).
IC compiler II delivers first-pass silicon success
Synopsys has announced that Graphcore achieved first-pass silicon success using an IC Compiler II place-and-route solution, part of the Synopsys Fusion Platform, for designing its second-generation Colossus MK2 GC200 Intelligence Processing Unit (IPU), featuring 59.4 billion transistors, on a 7nm advanced process technology.
Silicon Lifecycle Management platform for SoC designs
Synopsys has unveiled its Silicon Lifecycle Management (SLM) platform, a data-analytics-driven approach to optimising SoCs from the design phase through to end-user deployment. The SLM platform, which is tightly coupled with Synopsys' market-leading Fusion Design Platform, will provide visibility into critical performance, reliability and security issues for the entirety of a chip's lifespan.
New Synopsys General Manager of the Digital Design Group
Synopsys has announced that Shankar Krishnamoorthy has been promoted to GM of the Digital Design Group. Krishnamoorthy, who rejoined Synopsys in 2017, is an electronic design automation veteran with 25 years of experience bringing to market high-value, market-leading physical design and logic synthesis solutions.
Synopsys DesignWare CXL IP supports AMBA CXS protocol
Synopsys has announced that its DesignWare CXL Controller IP now supports the AMBA CXS protocol, enabling an efficient interface with the latest, highly scalable Arm Neoverse Coherent Mesh Network to provide an optimised multichip IP stack for a range of high-performance computing, datacenter, and networking system-on-chip (SoCs).
HAPS-80 prototyping to validate data flow processor IP
Synopsys has announced that NSITEXE adopted Synopsys HAPS-80 prototyping solution to develop their current and next-generation Data Flow Processor (DFP) IP portfolio. HAPS-80 delivers the high-performance needed for software development and system validation of NSITEXE's RISC-V based accelerator with a complex 512-bit vector processing unit for vehicle control microcomputers.
Synopsys appoints Sassine Ghazi as Chief Operating Officer
Synopsys has announced that Sassine Ghazi has been appointed as Chief Operating Officer. Ghazi, who joined Synopsys in 1998, brings multiple decades of experience in chip design, applications engineering, customer support, sales, and business management.
Silicon-proven DesignWare Interface IP to accelerate SoCs
Synopsys has announced that JLQ Technology has selected Synopsys DesignWare Interface IP to accelerate development of its new generation of high-performance, low-power systems-on-chips (SoCs) for a range of applications.
Synopsys awarded DARPA contract for AISS program
Synopsys has announced that the Defense Advanced Research Projects Agency (DARPA) has selected Synopsys as a prime contractor for the Automatic Implementation of Secure Silicon AISS program. The program's goal is to automate the inclusion of scalable hardware security mechanisms in IP and system-on-chips (SoCs) to explore security versus other design trade-offs.
Highly scalable timing signoff flow in the cloud
Synopsys has announced that its collaboration with TSMC and Microsoft has delivered a highly scalable timing signoff flow for use in the cloud. This extensive, multi-month collaboration among the three industry partners speeds up the path to signoff next-generation systems-on-chips (SoCs).
Synopsys acquires analytics innovator Qualtera
Synopsys has announced it has acquired Qualtera, a fast-growing provider of collaborative high-performance, big data analytics for semiconductor test and manufacturing.
Synopsys enables Arm's next generation of mobile IP
Synopsys has announced that it has collaborated with Arm to enable tapeouts of optimised system-on-chips (SoCs) for early adopters of Arm's latest mobile IP, including Arm Cortex-A78 and Cortex-X1 CPUs, and Mali-G78 GPU.
Collaboration enables designs on TSMC N5 and N6 processes
Synopsys has announced certification of its digital and custom design platforms for TSMC's N5 and N6 process technologies. Synopsys' long-term collaboration with TSMC has resulted in accelerating next-generation product design for key vertical markets, including high-performance computing (HPC), mobile, 5G, and AI chip designs.
COVID-19 tracing app fails NHS and cyber security tests
It has been reported that the government’s anticipated COVID-19 tracing app has failed crucial security tests and is not yet safe enough to be rolled out across the UK. It is understood the system has failed all tests needed in order for it to be included in the NHS Apps Library, including cyber security, clinical safety and performance.
Synopsys’ ARC processor IP delivers performance boost
Synopsys has announced the new DesignWare ARC HS5x and HS6x processor IP families for high-performance embedded applications. The 32-bit ARC HS5x and 64-bit HS6x processors, available in single-core and multicore versions, are implementations of a new superscalar ARCv3 Instruction Set Architecture (ISA) and deliver up to 8750 DMIPS per core in 16-nm process technologies under typical conditions, making them the highest performance ARC processors ...