Synopsys Inc

Address:
700 East Middlefield Road
Mountain View

CA 94043
United States of America

Phone: 001 650 584-5000

Web: www.synopsys.com


Synopsys Inc articles

Displaying 1 - 20 of 590

Synopsys and Helic together deliver analogue and RF custom design flow

Synopsys and Helic together deliver analogue and RF custom design flow
Synopsys and Helic has announced that the companies have collaborated to integrate Helic's VeloceRF RF device synthesis, RaptorX EM modeling and Exalto EM parasitic extraction and signoff tools with Synopsys' Custom Design Platform. The result of the collaboration is a complete solution for electromagnetic-aware (EM-aware) layout and analysis of mixed-signal, analogue, and RF designs.
18th December 2017

Complete HDMI 2.1 IP solution with HDCP 2.2 content protection

Complete HDMI 2.1 IP solution with HDCP 2.2 content protection
Synopsys has announced its complete DesignWare HDMI 2.1 IP solution with High-Bandwidth Digital Content Protection (HDCP) 2.2 consisting of controllers, PHYs, verification IP, IP Prototyping Kit, and IP Subsystem as well as Linux software drivers. The IP supports advanced HDMI 2.1 features like fixed-rate link allowing uncompressed 8K resolution with 60Hz refresh rate for a more immersive viewing experience in digital TVs, AR/VR devices, and computer displays.
1st December 2017

Synopsys accelerates FIPS 140-2 certification

Synopsys accelerates FIPS 140-2 certification
Synopsys has announced it has successfully validated the DesignWare Cryptography Software Library through the National Institute of Standards and Technology (NIST) Cryptographic Algorithm Validation Program (CAVP). To earn validation, the DesignWare Cryptography Software Library passed a full suite of validation tests for secure functions including block ciphers (AES, DES), digital signatures (RSA and ECC based), secure hashing (SHA-1, 2 and 3) and random number generation.
2nd November 2017


Verification platform selected for RISC-V processor designs

Verification platform selected for RISC-V processor designs
  Fabless provider of customised, open-source-enabled semiconductors, SiFive, has selected the Synopsys Verification Continuum platform as its verification solution. SiFive has deployed the Verification Continuum platform for simulation, verification IP, debug, static verification and formal coverage closure.
30th October 2017

IP solution offers 300GB/s bandwidth for graphics SoCs

IP solution offers 300GB/s bandwidth for graphics SoCs
Provider of high-quality, silicon-proven IP solutions for SoC designs, Synopsys, has introduced its complete DesignWare High Bandwidth Memory 2 (HBM2) IP solution consisting of controller, PHY and verification IP, enabling designers to achieve up to 307GB/s aggregate bandwidth, which is 12 times the bandwidth of a DDR4 interface operating at 3,200Mb/s data rate. In addition, the DesignWare HBM2 IP solution delivers approximately ten times better energy efficiency than DDR4.
3rd August 2017

Prototyping system chosen for next-gen SoCs

Prototyping system chosen for next-gen SoCs
It has been announced by Synopsys that MediaTek, a fabless semiconductor company, has adopted Synopsys' HAPS-80 prototyping system, part of the Verification Continuum Platform, for their broad portfolio of next-gen system-on-chips (SoCs). Verification Continuum is built from Synopsys' verification technologies providing virtual prototyping, static and formal verification, simulation, verification IP, emulation, prototyping and debug.
2nd August 2017

Synopsys VC Formal selected for property verification

Synopsys has announced that Kyocera has selected Synopsys' VC Formal solution for high-performance formal property verification of their Multi-Functional Product (MFP) designs. Kyocera used VC Formal's next-generation high-performance formal engines and heuristic performance algorithms to achieve faster formal property verification.
28th June 2017

Vision Processor improves machine learning applications

Synopsys has announced that it has enhanced the convolutional neural network (CNN) engine in its DesignWare EV6x Vision Processors to address the increasing video resolution and frame rate requirements of high-performance embedded vision applications. The CNN engine delivers up to 4.5 TeraMACs per second when implemented in 16-nanometer (nm) FinFET process technologies under typical conditions, four times more performance than Synopsys' previous CNN engine.
27th June 2017

Toshiba selects Synopsys' VC Formal as SVA-based formal verification solution

Toshiba has deployed Synopsys' VC Formal solution as its SystemVerilog Assertion (SVA) based formal verification solution. VC Formal delivers the performance and capacity necessary to achieve faster formal convergence on Toshiba's increasingly complex designs. Toshiba leveraged VC Formal's native integration with Synopsys' industry-leading VCS functional verification solution and Verdi debug platform to achieve faster coverage closure, more effective root-cause analysis, and earlier verification closure.
22nd June 2017

Verification IP test suite delivered for ARM AMBA

Availability of its Verification IP (VIP) and source code test suite for ARM AMBA 5 Coherent Hub Interface (CHI) Issue B has been announced by Synopsys. The company’s VC VIP for AMBA CHI has been widely adopted by SoC leaders for successful verification closure and tape out of coherent subsystems and interconnects.
22nd June 2017

Synopsys VC Formal standardised for faster verification

Synopsys has announced that as their formal verification solution for advanced microcontroller designs, STMicroelectronics selected and standardised on Synopsys VC Formal.
9th June 2017

Solution enables cache coherency for high performance SoCs

Synopsys has announced the availability of its complete DesignWare CCIX IP solution, consisting of controller, PHY and verification IP delivering data transfer speeds up to 25Gbps and supporting cache coherency for high performance cloud computing applications.
8th June 2017

Duo accelerates adoption of advanced security platforms

Duo accelerates adoption of advanced security platforms
A new collaboration has been announced between Rambus and Synopsys to accelerate the adoption of advanced security platforms and technologies to protect valuable assets during key and device provisioning. As part of this collaboration, Rambus will provide its CryptoManager infrastructure and key provisioning services to support Synopsys DesignWare tRoot Hardware Secure Modules (HSMs) with Root of Trust, enabling secure remote lifecycle management of connected devices.
7th June 2017

Collaboration demonstrates full system interoperability

Collaboration demonstrates full system interoperability
In order to successfully demonstrate full system interoperability between Synopsys and Mellanox Technologies' two independently developed PCI Express 4.0 solutions, the companies have collaborated together. The demonstration includes a host, which contains the DesignWare Root Port Controller IP for PCI Express 4.0 specification in a DesignWare IP Prototyping Kit, connected to the Mellanox ConnectX-5 network adapter as a device. 
6th June 2017

Design and verification tools enable successful tape-outs

Early collaboration with ARM on Synopsys' latest IP targeted at artificial intelligence applications, including the ARM Cortex-A75 and Cortex-A55 Central Processing Units (CPUs), the first based on ARM DynamIQ technology, and the ARM Mali-G72 Graphics Processing Unit (GPU), has resulted in successful early adopter tape-outs in advanced FinFET process technologies using Synopsys' Design Platform and Verification Continuum Platform.
31st May 2017

Synopsys enters into $100m ASR

Synopsys enters into $100m ASR
  In order to repurchase an aggregate of $100m of Synopsys stock, Synopsys has entered into an accelerated share repurchase agreement (ASR) with JPMorgan Chase Bank, National Association. The agreement is in addition to Synopsys' two previous $100m ASRs in 2017 that were settled on 17th May 2017 and 16th February 2017.
31st May 2017

IC Validator certified by Samsung

  Synopsys has announced that its IC Validator physical signoff solution has been certified by Samsung Electronics for physical signoff of all designs using the 10LPP process technology. Samsung's foundry customers now have access to the speed and scalability advantages of IC Validator and can verify their designs with full confidence.
25th May 2017

Improved design supports Samsung's latest foundry processes

Synopsys has announced that Samsung Electronics has enabled the Synopsys Design Platform for Samsung's 8LPP (Low-Power Plus) and 7LPP process technologies. Samsung's 8LPP, a process derivative of 10LPP, offers smaller area when compared to 10LPP with minimal impact to the 10-nm design methodology. Synopsys Design Platform, silicon-proven at 10LPP, is being confidently deployed by early adopters of the 8LPP and 7LPP processes.
25th May 2017

Multi-protocol IP reduces power and area by over 35%

Multi-protocol IP reduces power and area by over 35%
  Suitable for high-performance computing applications including machine learning and artificial intelligence, Synopsys has announced its new DesignWare Multi-Protocol 25G PHY IP. The PHY IP gives designers the flexibility to efficiently integrate multiple protocols including PCI Express 4.0, 25G Ethernet, SATA and CCIX into system-on-chips (SoCs) targeting the 7 and 16nm FinFET processes.
24th May 2017

Collaboration to deliver complete hardware/software Root of Trust solution

InfoSec Global and Synopsys have announced a collaboration to provide a comprehensive, embedded Root of Trust solution that integrates InfoSec Global's Agile Cryptography capabilities with Synopsys' DesignWare tRoot Hardware Secure Module. The combined solution will provide designers with the programming interfaces needed to customize and differentiate their system-on-chips (SoCs) for highly secure industrial IoT applications such as programmable logic controllers, Supervisory Control and Data Acquisition (SCADA) and Distributive Control Systems (DCS).
11th May 2017


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