Synopsys Inc

Address:
700 East Middlefield Road
Mountain View

CA 94043
United States of America

Phone: 001 650 584-5000

Web: www.synopsys.com


Synopsys Inc articles

Displaying 1 - 20 of 606

Partnership to expand electronic design automation collaboration

Partnership to expand electronic design automation collaboration
It has been announced by Synopsys and Siemens PLM Software, that they have agreed to collaborate on a wide range of electronic design automation (EDA) product interoperability projects for the benefit of their mutual customers. The collaboration spans a number of EDA domains from design to verification.
4th July 2018

ASIP designer tools enable fast development of custom processor

ASIP designer tools enable fast development of custom processor
It has been announced by Synopsys, that RIKEN has successfully developed its high-performance application specific instruction set processor (ASIP) core for its molecular dynamics (MD) simulator using, by Synopsys' ASIP Designer tool.
29th June 2018

Power analysis to accelerate robust SoC design

Power analysis to accelerate robust SoC design
It has been announced by Synopsys that they are introducing PrimePower, an expanded power analysis solution created to accelerate system-on-chip (SoC) design closure by extending signoff power analysis to drive early design implementation and accurate reliability analysis. 
25th June 2018


Collaboration to accelerate 3D flash memory verification

Collaboration to accelerate 3D flash memory verification
A collaboration has been announced by Synopsys with Toshiba Memory to accelerate the verification of Toshiba Memory BiCS FLASH vertically stacked 3D flash memory. By working closely with Toshiba Memory, Synopsys introduced innovative simulation algorithms in its FineSim Pro FastSPICE tool to address the increased design complexity of 3D NAND Flash memory. These new technologies improve simulation speed by an average of 2X, thereby reducing multi-day simulation runs to less than a day.
13th June 2018

IC validator certified by GLOBALFOUNDRIES for physical verification

Synopsys, Inc. has announced that GLOBALFOUNDRIES (GF) has certified the Synopsys IC Validator tool for physical signoff on the GF 14LPP process technology. With this signoff certification, designers can take advantage of IC Validator's speed and scalability, while ensuring a high level of manufacturability compliance and maximum yield. The certified runsets, including DRC, LVS, and metal fill technology files, are available from GF.
15th May 2018

HAPS prototyping family has latest desktop prototyping solution

HAPS prototyping family has latest desktop prototyping solution
Synopsys, Inc. has announced the availability of its HAPS-80 Desktop (HAPS-80D) system for mid-range SoC prototyping. The Synopsys HAPS-80D system builds on the HAPS-80 prototyping family, with more than 1,500 systems deployed. HAPS-80D delivers high-performance prototyping with built-in interfaces for immediate design interaction to accelerate software development and system validation.
25th April 2018

Design optimisation for next-gen high-performance computing

Synopsys, Inc., in collaboration with ANSYS, has announced the immediate availability of RedHawk Analysis Fusion, a complete in-design power integrity add-on solution for Synopsys IC Compiler II place-and-route system users. Synopsys brings to production a fully integrated rail analysis flow that leverages IC Compiler II's best in-class power, performance, and area (PPA) with industry-standard RedHawk rail analysis from ANSYS.
20th March 2018

Fusion tech to transform the RTL-to-GDSII flow

Synopsys, Inc. has unveiled its breakthrough Fusion Technology that transforms the RTL-to-GDSII design flow with the fusion of best-in-class optimisation and industry-golden signoff tools, enabling designers to accelerate the delivery of their next-generation designs with industry-best full-flow quality-of-results (QoR) and the fastest time-to-results (TTR).
20th March 2018

New algorithms added to DesignWare security protocol

New algorithms added to DesignWare security protocol
Synopsys has announced that it has added the ChaCha20 and Poly1305 (RFC7539) algorithms to its DesignWare Multipurpose Security Protocol Accelerator IP, enabling designers to efficiently implement the latest encryption and authentication functionality to protect their IoT SoCs. The Security Protocol Accelerator IP increases security protocol performance by supporting efficient data sequencing as well as parallel processing of cryptographic operations such as authentication and encryption/decryption.
15th March 2018

High performance solution meets embedded applications

High performance solution meets embedded applications
Synopsys has announced the availability of the complete Universal Flash Storage (UFS) IP solution, compliant with the latest JEDEC UFS v3.0 standard. The high-throughput, low latency DesignWare UFS 3.0 IP solution doubles the bandwidth to 11.6Gbps per lane for a faster interface between SoCs and storage ICs, compared to UFS 2.1. The power efficient MIPI M-PHY delivers less than 3.5mW/Gbps per lane by supporting a range of burst modes and power management modes with fast recovery time.
14th March 2018

Software security solutions on show at embedded world 2018

Software security solutions on show at embedded world 2018
At the embedded world 2018 conference in Nuremberg, Germany, taking place 27th February to 3rd March, Synopsys will showcase its electronic design, IP, and application security solutions. During the conference, Synopsys will also host Elevate, an evening thought-leadership event featuring a group of international cyber security experts leading a discussion about IoT and embedded systems security threats and solutions. Elevate is free and open to all conference attendees but space is limited.
16th February 2018

Dev kit accelerates software development for ARC-based systems

Dev kit accelerates software development for ARC-based systems
In order to accelerate software development for the ARC HS processor family, Synopsys has announced availability of the DesignWare ARC HS Development Kit. The ARC HS Development Kit is a ready-to-use software development platform that includes access to the embARC open source software packages on the embARC website, enabling designers to start software development prior to SoC availability.
12th February 2018

Verification IP and test suite for Arm AMBA ACE5 launched

Verification IP and test suite for Arm AMBA ACE5 launched
  Synopsys has announced availability of its Verification IP (VIP) and source code Test Suite for Arm AMBA ACE5 (AXI Coherency Extensions) and AXI5. Synopsys has collaborated with Arm to deliver the next-gen ACE5 and AXI5 VIP with increased performance for faster verification closure.
8th February 2018

Synopsys expands Coverity support for programming languages

Synopsys expands Coverity support for programming languages
  Synopsys has announced its Coverity 2018.01 release, the newest version of its static analysis tool, which analyses source code to detect critical quality and security defects early in the software development life cycle. Coverity 2018.01 extends the tool’s support for new programming languages, coding standards, and development tool integrations.
1st February 2018

Sensor interface modules reduce BoM and design time

Sensor interface modules reduce BoM and design time
Provider of RF modules and wireless connectivity solutions, Radiocrafts AS, has announced two new Sigfox modules, both with integrated sensor interfaces. The new modules are suitable for making a Low Power Wide Area Network (LPWAN) with wireless sensors. The RC1682-SSM and RC1692HP-SSM are both an expansion of the RC1682-SIG and RC1692HP-SIG modules released in 2015.
30th January 2018

Vision processor IP accelerates deep learning algorithms

Vision processor IP accelerates deep learning algorithms
Synopsys has announced that Inuitive selected Synopsys' DesignWare EV62 Embedded Vision Processor IP for its production NU4000 system-on-chip (SoC), which Inuitive claims to be its most advanced 3D imaging and vision SoC. Inuitive adopted the EV62 Processor IP to take advantage of the high performance and processing efficiency of the tightly integrated vector DSPs and convolutional neural network (CNN) engine.
23rd January 2018

Synopsys and Helic together deliver analogue and RF custom design flow

Synopsys and Helic together deliver analogue and RF custom design flow
Synopsys and Helic has announced that the companies have collaborated to integrate Helic's VeloceRF RF device synthesis, RaptorX EM modeling and Exalto EM parasitic extraction and signoff tools with Synopsys' Custom Design Platform. The result of the collaboration is a complete solution for electromagnetic-aware (EM-aware) layout and analysis of mixed-signal, analogue, and RF designs.
18th December 2017

Complete HDMI 2.1 IP solution with HDCP 2.2 content protection

Complete HDMI 2.1 IP solution with HDCP 2.2 content protection
Synopsys has announced its complete DesignWare HDMI 2.1 IP solution with High-Bandwidth Digital Content Protection (HDCP) 2.2 consisting of controllers, PHYs, verification IP, IP Prototyping Kit, and IP Subsystem as well as Linux software drivers. The IP supports advanced HDMI 2.1 features like fixed-rate link allowing uncompressed 8K resolution with 60Hz refresh rate for a more immersive viewing experience in digital TVs, AR/VR devices, and computer displays.
1st December 2017

Synopsys accelerates FIPS 140-2 certification

Synopsys accelerates FIPS 140-2 certification
Synopsys has announced it has successfully validated the DesignWare Cryptography Software Library through the National Institute of Standards and Technology (NIST) Cryptographic Algorithm Validation Program (CAVP). To earn validation, the DesignWare Cryptography Software Library passed a full suite of validation tests for secure functions including block ciphers (AES, DES), digital signatures (RSA and ECC based), secure hashing (SHA-1, 2 and 3) and random number generation.
2nd November 2017

Verification platform selected for RISC-V processor designs

Verification platform selected for RISC-V processor designs
  Fabless provider of customised, open-source-enabled semiconductors, SiFive, has selected the Synopsys Verification Continuum platform as its verification solution. SiFive has deployed the Verification Continuum platform for simulation, verification IP, debug, static verification and formal coverage closure.
30th October 2017


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