Synopsys demonstrates interoperability with Intel
Synopsys has announced that its collaboration with Intel has achieved end-to-end 64 GT/s interoperability between Synopsys’ IP for PCI Express (PCIe) 6.0 and Intel’s PCIe 6.0-enabled test chip.
This milestone validates that future products integrating PCIe 6.0 solutions from Synopsys or Intel will communicate effectively with the ecosystem, reducing design risk and accelerating time-to-market.
The demo, showcasing successful interoperability between the Synopsys endpoint PHY and Controller IP for PCIe 6.0 and Intel PCIe 6.0 test chip, will be featured in the CXL, PCIe and DRAM Emerging Technologies Community at Intel Innovation 2023, taking place 19—20 September 2023. Synopsys’ complete IP solution for PCIe 6.0 includes controllers, PHYs, verification IP, and integrity and data encryption (IDE) security IP to accelerate development of chips for high-performance computing and AI applications.
“Our decades-long collaboration with Intel has empowered designers to implement the latest industry standards using trusted Synopsys IP,” said John Koeter, Senior Vice President of Marketing and Strategy for IP at Synopsys. “The successful interoperability with Intel, combined with more than two dozen PCIe 6.0 design wins, validates the robustness of the silicon-proven Synopsys IP for PCIe 6.0 and enables designers to reduce integration risk, meet stringent requirements, and accelerate their time to market.”
“To meet the demands of data-intensive operations in the cloud and on the edge, designers require advanced connectivity and processing technologies that operate with low latency at fast speeds,” said Debendra Das Sharma, Senior Fellow and co-GM of Memory and I/O Technologies at Intel Corporation. “Intel’s close collaboration with Synopsys, a leading PCIe IP provider, has once again resulted in successful interoperability using the latest PCIe standard. Our intent with this demonstration is to give the ecosystem confidence that Intel’s future generation products with PCIe 6.0 will be interoperable with the ecosystem, enabling broad adoption of the PCIe 6.0 standard.”