Cadence announced the immediate availability of verification IP (VIP) for ARM Ltd.’s new AMBA 4 Coherency Extensions protocol (ACE), extending its popular VIP catalog and speeding the development of multiprocessor mobile devices.

Cadence today announced that technology leader Samsung Electronics, Co., Ltd. deployed the Cadence unified digital flow, from RTL to GDSII, to tape out a test chip at 20 nanometers. The Cadence Encounter-based flow and methodology were integrated to address the requirements of Samsung’s advanced 20-nanometer process technology for the test chip. The flow handled IP integration and validation, as well as the complex design rules at 20 nanometers...

Cadence announced it has acquired Azuro, Inc., a company that has pioneered a paradigm shift in the digital implementation and optimization of next-generation SoCs. Azuro offers unique clock concurrent optimization technology, also known as ccopt, which delivers superior capabilities for designers faced with increasing performance, power and area challenges.

Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today unveiled OrCAD Capture Marketplace, a unique Web-enabled environment that brings a complete PCB ecosystem—including an industry-first online store for applications—to engineers’ fingertips.

Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced it has acquired Altos Design Automation, Inc., the technology leader in enabling foundation IP development for the delivery of complex SoCs at advanced nodes. Shrinking process geometries increase process variations and make creation of accurate noise, power and timing models for foundation IP very complex given smaller time-to-market wi...

Cadence Design Systems today announced that Robert Bosch GmbH (Bosch) has standardized on an enhanced custom/analog flow based on Cadence® Virtuoso® v6.1 technology, gaining approximately a 25 percent advantage in productivity for advanced custom/analog silicon design.

Cadence reported first quarter 2011 revenue of $266 million, compared to revenue of $222 million reported for the same period in 2010. On a GAAP basis, Cadence recognized net income of $6 million, or $0.02 per share on a diluted basis in the first quarter of 2011, compared to a net loss of $12 million, or $(0.04) per share on a diluted basis, in the same period in 2010.

Cadence Design Systems introduced the latest version of its Allegro PCB and IC packaging technology, delivering new capabilities that provide a significant increase in both productivity and predictability across silicon, SoC and system development.

Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, inaugurates its annual series of technical user conferences with CDNLive! EMEA (Europe, Middle East, and Africa), to be held May 3-5 at the Dolce Hotel in Munich. The worldwide CDNLive! events bring together thousands of Cadence® technology users, developers, and industry experts to examine challenges and synthesize solutions for developing innovative e...

Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced a comprehensive DDR4 solution that will enable SoC designers to take immediate advantage of the performance gains afforded by the emerging DDR4 memory standard.

Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced that it is first to market with a licensable, wide I/O memory controller core, along with an integration environment, that brings PC-like performance to mobile applications like smartphones and tablets.

Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global design innovation, today announced that CERN, the European Organization for Nuclear Research, is relying on Cadence ® Services to create and maintain design environments for internal design teams as well as for design teams in a number of collaborating physics institutes throughout Europe and the United States.

Cadence Design Systems Inc detailed the extensive expansion of its broad portfolio of verification IP and memory models, which delivers a robust verification solution spanning silicon, SoC and system development. The Cadence VIP offering boasts support of new protocols such as ARM AMBA 4 and MIPI to address early IP verification and integration through to system validation in demonstration of the EDA360 vision. In addition to memory models and VI...

Cadence today announced that IMS CHIPS has adopted Cadence® Silicon Realization technologies for its special mixed-signal gate array technology. IMS CHIPS plans to deploy Cadence end-to-end Virtuoso® custom and Encounter® digital technologies for its commercial research business in areas such as advanced silicon technology, customer-specific circuits, nanopatterning and image sensor technology.

Cadence Design Systems today announced that Broadcom Corporation, a global leader in semiconductors for wired and wireless communications, is expanding its use of the Cadence® Verification Computing Platform, Palladium® XP, to help validate its complex system designs before committing them to silicon.

Cadence Design Systems today advanced the design of giga-gate/gigahertz system on chips (SoCs) with a proven digital end-to-end flow at 28 nanometers that yields both performance and time-to-market advantages. Driven by the Cadence Silicon Realization approach, the new Encounter-based flow provides a faster, more deterministic path to achieve giga-gate/gigahertz silicon through technology integration and significant core architecture and algorith...

Cadence Design Systems today announced that Spreadtrum Communications (NASDAQ: SPRD), a leading provider of baseband and RF processor solutions for the wireless communications market headquartered in Shanghai, migrated to the Cadence® Silicon Realization flow and successfully taped out its first 40-nanometer low-power chip. The chip, a GSM/GPRS/EDGE/TD-SCDMA/HSPA mobile phone baseband, was taped out with one-pass silicon success.

Cadence Design Systems today introduced a qualified 32/28-nanometer reference flow targeting Common Platform technology. Cadence® collaborated closely with members of the Common Platform alliance—IBM, GLOBALFOUNDRIES, and Samsung Electronics—to develop a comprehensive flow from RTL synthesis to GDSII signoff for the advanced node, low-power high-k metal gate (HKMG) process technology.

Cadence today announced significant new advancements to help boost verification productivity for ASIC and FPGA designers. Coupled with full support for the emerging Accellera Universal Verification Methodology (UVM) 1.0 industry standard, the 600-plus new capabilities expand the scope of metric-driven verification (MDV) to help engineers achieve faster, more comprehensive verification closure and Silicon Realization.

Cadence Design Systems announce that the Cadence Virtuoso Accelerated Parallel Simulator has won the Elektra Electronics Industry Awards 2010 as the best design tool and development software. The Elektra Awards, established in 2003 and organized by Electronics Weekly and Reed Business Information in Europe, gives the industry an opportunity to recognize the achievements of individuals and companies across Europe.