Cadence Design Systems, Inc. today announced TripleCheck IP Validator, a new addition to the Cadence Verification IP (VIP) Catalog that simplifies and accelerates compliance testing of interface design IP. The expanding Cadence VIP Catalog is helping leading system and semiconductor companies quickly and thoroughly verify their implementations of standard interfaces, such as PCI Express 3.0.

Cadence Design Systems, Inc. today announced results for the first quarter of fiscal year 2012. Cadence reported first quarter 2012 revenue of $316 million, compared to revenue of $266 million reported for the same period in 2011. On a GAAP basis, Cadence recognized net income of $31 million, or $0.11 per share on a diluted basis in the first quarter of 2012, compared to net income of $6 million, or $0.02 per share on a diluted basis in the same ...

Cadence Design Systems, Inc. today announced the addition of design intellectual property (IP) for the LPDDR3 mobile memory standard to the company’s design IP portfolio. Designed to provide the high bandwidth and low power consumption required by smartphones and tablets, the Cadence LPDDR3 memory IP solution includes integrated controller and PHY support, virtual prototyping, verification IP and Allegro design-in kits to accelerate implementat...

Cadence Design Systems, Inc. today introduced the latest release of Cadence Encounter RTL-to-GDSII flow for high-performance and giga-scale designs, including those at the latest technology node, 20 nanometers. Developed in close collaboration with leading IP and foundry partners and customers, the new RTL-to-GDSII design, implementation and signoff flow enables more efficient development of SoCs, meeting and exceeding the power, performance and ...

Cadence Design Systems, Inc. today announced that Samsung Electronics’ Foundry business, Samsung Foundry, has collaborated with Cadence to develop a world-class design-for-manufacturing (DFM) infrastructure to produce the most advanced chips. Working closely together, Cadence and Samsung Foundry have developed “in-design” and signoff DFM flows to tackle physical signoff and electrical variability optimization for 32-, 28- and 20-nanometer S...

Cadence reported fourth quarter 2011 revenue of $308 million, compared to revenue of $249 million reported for the same period in 2010. On a GAAP basis, Cadence recognized net income of $11 million, or $0.04 per share on a diluted basis in the fourth quarter of 2011, compared to a net loss of $37 million, or $(0.14) per share on a diluted basis in the same period in 2010.

Cadence Design Systems, Inc. today announced it has expanded its Flash IP offering to include support for the Open NAND Flash Interface (ONFI) 3.0 specification. Cadence is the first company to provide a combined ONFI 3 controller and PHY IP solution, significantly streamlining SoC and system design while ensuring an optimized ONFI 3 implementation for maximum performance. Cadence Flash IP, including the broad portfolio of Denali IP acquired in ...

Cadence Design Systems, Inc. has announced that Panasonic Corporation has deployed the Cadence Palladium XP Verification Computing Platform, part of the Cadence System Development Suite, to speed the design of Systems-on-Chip (SoCs) for next-generation digital consumer products such as Smart TVs and video recorders. Palladium XP unifies simulation, acceleration and emulation capabilities in a single environment enabling hardware-software system ...

Cadence Design Systems, Inc. has announced that QLogic has deployed the Cadence Palladium XP Verification Computing Platform to speed the design of a complex network switch. QLogic manufactures Fibre Channel, 10Gb Ethernet converged networking and InfiniBand switches for storage and high-performance computing (HPC) applications. These switches provide the port-density and performance required to drive storage, data and HPC networks of leading OEM...

Cadence Design Systems has joined the Higher Engineering Education Alliance Program (HEEAP) with an in-kind donation of electronic design automation (EDA) software and services valued at over USD $40 million. The donation enables students in Vietnam to gain hands-on experience with the software and services that engineers around the world rely on, including the Cadence proprietary software, hardware, design and verification IP, memory models, met...

Cadence Design Systems has announced the Call for Papers for its seventh annual user conference, CDNLive! EMEA, to be held in Munich, Germany, May 14-16, 2012. All Cadence technology users including IC and PCB designers, layout architects, verification and CAD engineers and project managers are invited to submit their abstracts. The submission deadline is December 14, 2011. According to this year’s theme Connect.Share.Inspire. participants hav...

Cadence reported third quarter 2011 revenue of $292 million, compared to revenue of $238 million reported for the same period in 2010. On a GAAP basis, Cadence recognized net income of $28 million, or $0.10 per share on a diluted basis in the third quarter of 2011, compared to net income of $127 million, or $0.48 per share on a diluted basis in the same period in 2010. GAAP net income for the third quarter of 2010 included $148 million in income ...

Xilinx and Cadence Design Systems have announced that they have teamed to develop the industry’s first virtual platform to enable system design, software development, and testing of Xilinx Zynq-7000 Extensible Processing Platform based systems in advance of hardware availability. This solution further enhances the development environment being put into place for Xilinx’s ARM processor-based processing platform and changes the development flow...

ARM and Cadence Design Systems, Inc. announced the tape out of the industry’s first 20nm design based on the ARM Cortex-A15 MPCore processor. The test chip, targeting TSMC’s 20nm process, was jointly developed by engineers from ARM, Cadence and TSMC using a Cadence RTL-to-signoff flow. Today’s milestone announcement is the result of an 18 month collaboration between ARM and Cadence on optimised design flows for the Cortex-A15 processor.

Cadence Design Systems, Inc. today announced that it has collaborated with TSMC to provide mutual customers access to a library characterization reference kit. The Cadence Library Characterizer (Altos Liberate) reference kit for TSMC’s standard cell libraries is now available to TSMC customers for download on TSMC-Online.

Cadence Design Systems announced that X-FAB has qualified the Cadence Physical Verification System (PVS) for the majority of its process technologies. Foundry qualification means that X-FAB has given its stamp of approval for silicon accuracy of the Cadence Physical Verification System across all of its process nodes, and that mixed-signal customers can reap new performance and productivity advantages enabled by its tight integration into the Cad...

Cadence Design Systems, Inc. announced new protocol and memory model verification IP (VIP) that will accelerate the adoption of the latest mobile standards. Through close collaboration with leading system and semiconductor companies, and standards bodies, Cadence is delivering VIP at a very early stage – in many cases, ahead of the final specification – helping mobile SoC and system manufacturers to be first to market with increasingly featur...

Cadence Design Systems, has appointed Alexander Duesener as vice president of EMEA (Europe, Middle East and Africa). In this role, Duesener will head the Cadence EMEA Field Operations, which includes sales, technical and customer support, and services. He will be based in Munich, Germany.

Cadence Design Systems, Inc. announced that Fujitsu Semiconductor Limited has adopted Cadence signoff design-for-manufacturing technologies for its complex 28-nanometer ASIC and system-on-chip mixed-signal designs. Deploying the Cadence DFM offerings helps Fujitsu Semiconductor engineers ensure high yield, predictability, and a faster path to Silicon Realization for next-generation chips that will serve as the brains of the company’s advanced c...

Cadence Design Systems announced that it has teamed with GLOBALFOUNDRIES to dramatically reduce the turnaround time for design-for-manufacturing (DFM) signoff at 28 nanometers. The companies’ advanced technologies enable customers to find and fix potential lithography hotspot problems that could reduce yield or even threaten viability of complex chip designs headed for manufacturing. Using the proven Cadence “in-design” DFM technology to s...