Cadence Acquires Azuro

Disruptive Technology Strengthens Cadence Digital Implementation Flow, Brings QoS in Power, Performance and Area to Next-gen SoC Designs.

Specifically, ccopt technology has delivered significant quality of silicon (QoS) on high-speed processor designs in the areas of:
Power (clock tree power reduction up to 30 percent and total power improvements of up to 10 percent),
Performance (improvements of up to 100 MHz for a GHz design), and
Area (clock tree area reduction up to 30 percent)
The acquisition was completed July 11, 2011, and is not expected to have a material effect on the Cadence’s results of operation for fiscal 2011. Terms of the acquisition were not disclosed. All key management, technical and key field applications personnel will transition to Cadence.

The Azuro ccopt technology is experiencing rapid adoption by designers implementing high-speed embedded processors and complex SoCs. The technology uniquely integrates and merges core steps in the flow including timing-driven placement, useful-skew clock tree synthesis, incremental physical optimization, physical clock gating, and post-clock tree optimization.

“Traditional digital implementation flows are reaching their limits in their ability to meet the power, performance and area requirements of today’s SoC designs,” said Chi-Ping Hsu, senior vice president, research and development, Silicon Realization Group at Cadence. “Azuro has invented a truly disruptive technology that goes far beyond traditional, multi-step and iterative digital implementation flows and provides significant advantages for both today’s complex silicon and SoC designs, as well as advanced-node, next-generation SoCs. We welcome this team to Cadence, and its innovative technology to our award-winning Encounter Digital Implementation flow.”

The acquisition, along with the recent acquisition of Altos, underscores the Cadence commitment to invest in and deliver the technologies that are needed to help customers realize next-generation SoC designs. The clock network is the heartbeat of any high-speed and/or low-power design and becomes critical to achieving power, performance and area targets for SoCs. In today's designs, there are often well over a hundred interlinked clock signals that can be branched and merged thousands of times, requiring a new design paradigm for digital implementation and optimization.

“Realizing the growing challenges of increasingly complex SoCs, Azuro pioneered a fundamentally new approach to digital implementation that took into account the critical role of clocks in achieving power, performance, and area specs,” said Paul Cunningham, co-founder and CEO of Azuro. “Cadence has been aggressively advancing its digital implementation solution and shares our view of the innovation that is required to continue to help customers realize the next generation of design. We look forward to joining the Cadence team to bring a new generation of digital implementation to the industry.”

The increasing challenges of SoC design were outlined in the Cadence vision for the industry, called EDA360.

Cadence will offer the Azuro ccopt technology immediately as an upgrade add-on for Cadence EDI customers.