Cadence Design Systems
Cadence Design Systems Articles
Accelerating hyperscale computing SoC design down to 4nm
Cadence Design Systems has announced that it has optimised the Cadence digital 20.1 full flow for Samsung Foundry’s advanced-process technologies down to 4nm. Through the collaboration, designers can use the Cadence tools to achieve optimal power, performance, and area (PPA) and deliver accurate, first-pass silicon for hyperscale computing applications.
Tensilica SoC using adaptive body bias feature
Cadence Design Systems has announced that it has collaborated with GLOBALFOUNDRIES (GF) to successfully tape out a Cadence Tensilica test chip on GF’s 22FDX platform. This design used the Cadence digital full flow with Adaptive Body Bias (ABB) foundation IP along with the popular Cadence Tensilica HiFi 5 and Fusion F1 DSPs, which are suited for high-growth markets including IoT, voice processing and always-on sensor fusion.
Cadence receives TSMC OIP award for N3 collaboration
Cadence Design Systems has announced that it has received a TSMC Open Innovation Platform (OIP) Ecosystem Forum Customers’ Choice award for a paper, ‘Optimised Digital Design, Implementation and Signoff on TSMC’s N3’, which was presented during the TSMC 2020 North America OIP Ecosystem Forum.
Cadence completes NUMECA International acquisition
Cadence Design Systems has acquired NUMECA International. The addition of NUMECA’s technologies and talent supports the Cadence Intelligent System Design strategy.
Advancing AI, ML and data analytics at MIT
Cadence has announced the establishment of the Cadence Design Systems Professorship Fund for the Massachusetts Institute of Technology (MIT) Stephen A. Schwarzman College of Computing.
Cadence acquires NUMECA to expand system analysis
Cadence Design Systems has entered into a definitive agreement to acquire NUMECA International, a specialist in computational fluid dynamics (CFD), mesh generation, multi-physics simulation and optimisation.
Samsung specifies Spectre X for 5nm PCIe PHY IP
Cadence Design Systems says that Samsung Foundry has adopted the Cadence Spectre X Simulator for its latest 5nm PCI Express(PCIe) PHY IP for automotive, mobile, consumer and healthcare applications.
Reducing mobile systems design cycle time
Cadence Design Systems has announced that L&T Technology Services Limited (LTTS) reduced its design cycle time for mobile camera and memory devices by three weeks, or nearly 40%, by adopting the Cadence Clarity 3D Solver to analyse complex high-speed interconnects, including both 10G and 25G Ethernet and MIPI signals.
Cadence Tensilica ConnX certification for V2X DSP IP
Cadence Design Systems has announced that the Cadence Tensilica ConnX B10 and ConnX B20 DSPs are DSPs optimised for automotive radar, lidar and vehicle-to-everything (V2X) to achieve Automotive Safety Integrity Level B in support of D (ASIL B(D))-compliant certification.
Vidatronic achieves speedup with Spectre X Simulator
Cadence Design Systems has announced that Vidatronic has successfully used the Cadence Spectre X Simulator to achieve electromigration and IR drop (EM-IR) reliability analysis on edge 7nm and 5nm analogue IP designs for mobile, hyperscale and other consumer electronics.
IC design flow certfied for Samsung's 3nm GAA process
Cadence Design Systems says that its custom and analog/mixed-signal (AMS) IC design flow has achieved certification for Samsung Foundry’s 3nm GAA process technology for early design starts.
Verification IP at chip level enables efficiency gains
Cadence Design Systems has released Cadence System-Level Verification IP (System VIP), a new suite of tools and libraries for automating system-on-chip (SoC) testbench assembly, bus and CPU traffic generation, cache-coherency validation and system performance bottleneck analysis.
Cadence unveils platform to slice EMI simulation costs
Cadence Design Systems is aiming to ease the frustrations of customers seeking to meet EMI emissions compliance.
Pegasus Verification System certified for TSMC N16, N12 and N7
Cadence Design Systems has announced that the Pegasus Verification System has achieved the latest Design Rule Manual (DRM) certification for the TSMC N16, N12 and N7 process technologies. The Cadence Pegasus Verification System has been successfully validated by TSMC to provide customers with a fast path to meet physical verification signoff goals across several application areas including AI, automotive, processor, data center and IP application...
Cadence GDDR6 IP family is silicon proven for TSMC N6
Cadence Design Systems has announced that Cadence GDDR6 IP is silicon proven on TSMC’s N6, immediately available on both N6 and N7 and forthcoming for TSMC N5 process technologies. The GDDR6 IP consists of Cadence PHY and controller Design IP and Verification IP (VIP) that is targeted at very high-bandwidth memory applications.
Complete DDR5/LPDDR5 IP solution for TSMC N5
Cadence Design Systems has announced the immediate availability of a complete, silicon-proven Cadence DDR5/LPDDR5 IP supporting the DDR5 and LPDDR5 DRAM memory standards on TSMC N5 process. The multi-standard IP includes Cadence PHY and controller Design IP and Verification IP (VIP) and supports a wide variety of applications including data center, storage, artificial intelligence/machine learning (AI/ML) and hyperscale computing.
Mixed-signal OpenAccess PDK for 22FDX platform
Cadence Design Systems has announced a collaboration with GLOBALFOUNDRIES (GF) that resulted in the availability of a Mixed-Signal OpenAccess PDK (process design kit) that supports GF’s 22FDX platform. To advance the adoption of the 22FDX platform and help customers speed time to market, the PDK ensures that the qualified Cadence digital, custom and RF design tools interoperate with the GF 22FDX platform, simplifying next-generation 5G mmWa...
Cadence, GloFo collaborate on 12LP/12LP+ Solutions
Cadence Design Systems has announced a broad IP collaboration with GLOBALFOUNDRIES (GF) on the 12LP platform and 12LP+ solution encompassing support for advanced memory interfaces including DDR4, DDR5, GDDR6, LPDDR4X and LPDDR5.
UltraLink D2D PHY IP on TSMC N7, N6 and N5 processes
Cadence Design Systems has announced the availability of its silicon-proven Cadence UltraLink D2D PHY IP on the TSMC N7 process. Test silicon on the TSMC N7 process with full silicon characterisation data is now available, for very high-speed, advanced IP. Extensive silicon validation is necessary to guarantee design margins, performance across all process corners, bit-error rate (BER), insertion loss and maximum transmission speed.
Custom flows achieve certification for TSMC N3 process
Cadence Design Systems has announced that its digital full flow and custom tool suite has been optimised for TSMC’s 3nm (N3) process technology. The Cadence tools have achieved the latest Design Rule Manual (DRM) and SPICE certification for TSMC’s N3 process.