Cadence Design Systems

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Cadence Design Systems Articles

Displaying 1 - 20 of 455
24th July 2020
mmWave reference flow on 28HPC+ Process technology

Cadence Design Systems and United Microelectronics Corporation have announced that the Cadence millimetre wave (mmWave) reference flow has achieved certification for UMC’s 28HPC+ process technology.

17th June 2020
Collaboration uses cloud to cut IC design schedules

Cadence Design Systems has revealed the results of a three-way collaboration with TSMC and Microsoft focused on utilising cloud infrastructure to reduce semiconductor design signoff schedules.

15th June 2020
FPGAs for edge computing use digital full flow solution

Cadence Design Systems has announced that Efinix successfully utilised the Cadence digital full flow solution to complete the first wave of its Trion family of field programmable gate arrays (FPGAs), which are used in edge compute, AI/ML and vision processing applications for the mobile, industrial and surveillance markets.

5th June 2020
3D analysis tool shortens AI vision design cycle

Ambarella has adopted the Cadence Clarity 3D Solver for design of their next-generation AI vision processors.

3rd June 2020
Custom/analogue EDA flow certification for TSMC N6

Cadence Design Systems has announced that its digital full flow and custom/analogue tool suites have been further enhanced to deliver optimal results on TSMC’s N6 and N5 process technologies. The Cadence tool suites have achieved Design Rule Manual (DRM) and SPICE certification for TSMC’s latest N6 and N5 process technologies.

27th May 2020
Cadence optimises digital full flow for Arm Cortex-A78

Cadence Design Systems has announced that it has broadened its long-standing collaboration with Arm to advance the development of mobile devices based on the Arm Cortex-A78 and Cortex-X1 CPUs.

21st May 2020
Verification IP solutions meet latest standards protocols

Ten new Verification IP (VIP) solutions that allow engineers to quickly and effectively verify their designs to meet the specifications for the latest standards protocols have been released by Cadence Design Systems.

18th March 2020
Digital full flow optimised to deliver improved quality

The latest release of the Cadence digital full flow—proven with hundreds of completed advanced-node tapeouts—has been enhanced to further optimise power, performance and area (PPA) results across a variety of application areas including automotive, mobile, networking, high-performance computing and artificial intelligence (AI).

11th March 2020
Optimised software for DSPs accelerates AI development

Optimised software for Cadence Tensilica HiFi digital signal processors (DSPs) efficiently executes TensorFlow Lite for Microcontrollers, part of the TensorFlow end-to-end open-source platform for machine learning (ML) from Google.

10th March 2020
Cadence, STMicro partner for VSR SerDes 7nm tape out

Cadence Design Systems has been working together with STMicroelectronics to successfully tape out a 56G very short-reach (VSR) SerDes in 7nm for a system on chip (SoC) targeted at the networking, cloud and data centre markets.

14th January 2020
Cadence, Broadcom to collaborate on 5nm designs

Cadence Design Systems and Broadcom have extended their collaboration to create semiconductor solutions targeting next-generation networking, broadband, enterprise storage, wireless and industrial applications. Following successful 7nm designs, the companies will now work on creating 5nm designs using Cadence digital implementation solutions.

8th January 2020
LC3 code implemented for Bluetooth LE audio

An implementation of the Low Complexity Communications Codec (LC3) that is expected to be compliant with LE Audio, the next generation of Bluetooth audio, is available now for Cadence Tensilica HiFi DSPs and has been delivered to a lead customer.

11th December 2019
Design tools enable first pass silicon success

Cadence Design Systems says that Global Unichip Corporation (GUC) successfully deployed the Cadence digital implementation and signoff flow and delivered advanced-node (N16, N12 and N7) designs for artificial intelligence (AI) and high-performance computing (HPC) applications.

3rd December 2019
Cadence pays $160m to buy AWR from National Instruments

Cadence Design Systems is buying RF EDA software specialist AWR from National Instruments (NI) for $160m. The acquisition is the latest building block in Cadence’s Intelligent System Design strategy which helps engineers deal with major design and implementation decisions from system to silicon.

16th November 2019
Low-latency interface shortens development cycles

The Cadence UltraLink D2D PHY IP from Cadence Design Systems is a high-performance, low-latency PHY for die-to-die connectivity targeted at the AI/ML, 5G, cloud computing and networking market segments.

6th November 2019
Integrated power integrity solution enables signoff at 7nm

A comprehensive static timing/signal integrity analysis and power integrity analysis tool, which enables engineers to create reliable designs at 7nm and below has been released by Cadence Design Systems. The Tempus Power Integrity Solution is the result of an integration between the Cadence Tempus Timing Signoff Solution and the Voltus IC Power Integrity Solution.

30th October 2019
Cadence corrals four partner awards from TSMC

Cadence Design Systems was presented with four TSMC Partner of the Year awards at the TSMC 2019 Open Innovation Platform (OIP) Ecosystem Forum. Cadence achieved recognition for the joint development of the N6 design infrastructure, SoIC design solution, cloud-based productivity solution and DSP IP.

25th October 2019
VIP for NVMe 1.4 eases path to SoC verification

What is said to be the industry’s first Verification IP (VIP) in support of the new NVM Express 1.4 (NVMe) protocol has been released by Cadence Design Systems. The Cadence VIP for NVMe 1.4 enables designers to quickly and thoroughly verify their storage, data centre and high-performance computing (HPC) system-on-chip (SoC) designs with less effort and a greater assurance that the SoC will meet the protocol standards.

9th October 2019
Cadence, Arm and Samsung deliver 5LPE Flow for “Hercules” CPU

Cadence Design Systems has collaborated with Samsung Foundry and Arm to deliver a complete, high-performance digital implementation and signoff full flow for the rapid implementation of the next-generation Arm “Hercules” CPU using the Samsung Foundry 5nm Low-Power Early (5LPE) process technology.

25th September 2019
Cadence design tools get thumbs-up from TSMC

Digital and signoff full flow and custom/analogue tools from Cadence Design Systems have achieved certification on TSMC’s N6 and N5/N5P process technologies. The Cadence tools have attained the latest N6 and N5/N5P Design Rule Manual (DRM) and SPICE certification, advancing next-generation mobile application development.

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