Cadence Design Systems
Cadence Design Systems Articles
Cadence Tensilica ConnX certification for V2X DSP IP
Cadence Design Systems has announced that the Cadence Tensilica ConnX B10 and ConnX B20 DSPs are DSPs optimised for automotive radar, lidar and vehicle-to-everything (V2X) to achieve Automotive Safety Integrity Level B in support of D (ASIL B(D))-compliant certification.
Vidatronic achieves speedup with Spectre X Simulator
Cadence Design Systems has announced that Vidatronic has successfully used the Cadence Spectre X Simulator to achieve electromigration and IR drop (EM-IR) reliability analysis on edge 7nm and 5nm analogue IP designs for mobile, hyperscale and other consumer electronics.
IC design flow certfied for Samsung's 3nm GAA process
Cadence Design Systems says that its custom and analog/mixed-signal (AMS) IC design flow has achieved certification for Samsung Foundry’s 3nm GAA process technology for early design starts.
Verification IP at chip level enables efficiency gains
Cadence Design Systems has released Cadence System-Level Verification IP (System VIP), a new suite of tools and libraries for automating system-on-chip (SoC) testbench assembly, bus and CPU traffic generation, cache-coherency validation and system performance bottleneck analysis.
Cadence unveils platform to slice EMI simulation costs
Cadence Design Systems is aiming to ease the frustrations of customers seeking to meet EMI emissions compliance.
Pegasus Verification System certified for TSMC N16, N12 and N7
Cadence Design Systems has announced that the Pegasus Verification System has achieved the latest Design Rule Manual (DRM) certification for the TSMC N16, N12 and N7 process technologies. The Cadence Pegasus Verification System has been successfully validated by TSMC to provide customers with a fast path to meet physical verification signoff goals across several application areas including AI, automotive, processor, data center and IP application...
Cadence GDDR6 IP family is silicon proven for TSMC N6
Cadence Design Systems has announced that Cadence GDDR6 IP is silicon proven on TSMC’s N6, immediately available on both N6 and N7 and forthcoming for TSMC N5 process technologies. The GDDR6 IP consists of Cadence PHY and controller Design IP and Verification IP (VIP) that is targeted at very high-bandwidth memory applications.
Complete DDR5/LPDDR5 IP solution for TSMC N5
Cadence Design Systems has announced the immediate availability of a complete, silicon-proven Cadence DDR5/LPDDR5 IP supporting the DDR5 and LPDDR5 DRAM memory standards on TSMC N5 process. The multi-standard IP includes Cadence PHY and controller Design IP and Verification IP (VIP) and supports a wide variety of applications including data center, storage, artificial intelligence/machine learning (AI/ML) and hyperscale computing.
Mixed-signal OpenAccess PDK for 22FDX platform
Cadence Design Systems has announced a collaboration with GLOBALFOUNDRIES (GF) that resulted in the availability of a Mixed-Signal OpenAccess PDK (process design kit) that supports GF’s 22FDX platform. To advance the adoption of the 22FDX platform and help customers speed time to market, the PDK ensures that the qualified Cadence digital, custom and RF design tools interoperate with the GF 22FDX platform, simplifying next-generation 5G mmWa...
Cadence, GloFo collaborate on 12LP/12LP+ Solutions
Cadence Design Systems has announced a broad IP collaboration with GLOBALFOUNDRIES (GF) on the 12LP platform and 12LP+ solution encompassing support for advanced memory interfaces including DDR4, DDR5, GDDR6, LPDDR4X and LPDDR5.
UltraLink D2D PHY IP on TSMC N7, N6 and N5 processes
Cadence Design Systems has announced the availability of its silicon-proven Cadence UltraLink D2D PHY IP on the TSMC N7 process. Test silicon on the TSMC N7 process with full silicon characterisation data is now available, for very high-speed, advanced IP. Extensive silicon validation is necessary to guarantee design margins, performance across all process corners, bit-error rate (BER), insertion loss and maximum transmission speed.
Custom flows achieve certification for TSMC N3 process
Cadence Design Systems has announced that its digital full flow and custom tool suite has been optimised for TSMC’s 3nm (N3) process technology. The Cadence tools have achieved the latest Design Rule Manual (DRM) and SPICE certification for TSMC’s N3 process.
IC packaging reference flow for TSMC solutions
Cadence Design Systems has announced the certification of the Cadence tools in TSMC reference flows for TSMC’s latest InFO and CoWoS advanced packaging solutions, the Integrated Fan-Out with RDL interconnect (InFO-R) and Chip-on-Wafer-on-Substrate with silicon interposer (CoWoS-S).
ML adds 5X faster verification closure to logic simulator
Machine learning technology (ML), dubbed Xcelium ML has been added to Cadence Design Systems’ Cadence Xcelium Logic Simulator to increase verification throughput.
mmWave reference flow on 28HPC+ Process technology
Cadence Design Systems and United Microelectronics Corporation have announced that the Cadence millimetre wave (mmWave) reference flow has achieved certification for UMC’s 28HPC+ process technology.
Collaboration uses cloud to cut IC design schedules
Cadence Design Systems has revealed the results of a three-way collaboration with TSMC and Microsoft focused on utilising cloud infrastructure to reduce semiconductor design signoff schedules.
FPGAs for edge computing use digital full flow solution
Cadence Design Systems has announced that Efinix successfully utilised the Cadence digital full flow solution to complete the first wave of its Trion family of field programmable gate arrays (FPGAs), which are used in edge compute, AI/ML and vision processing applications for the mobile, industrial and surveillance markets.
3D analysis tool shortens AI vision design cycle
Ambarella has adopted the Cadence Clarity 3D Solver for design of their next-generation AI vision processors.
Custom/analogue EDA flow certification for TSMC N6
Cadence Design Systems has announced that its digital full flow and custom/analogue tool suites have been further enhanced to deliver optimal results on TSMC’s N6 and N5 process technologies. The Cadence tool suites have achieved Design Rule Manual (DRM) and SPICE certification for TSMC’s latest N6 and N5 process technologies.
Cadence optimises digital full flow for Arm Cortex-A78
Cadence Design Systems has announced that it has broadened its long-standing collaboration with Arm to advance the development of mobile devices based on the Arm Cortex-A78 and Cortex-X1 CPUs.