Cadence Design Systems

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Phone: +44.1344.360333

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Web: www.cadence.com


Cadence Design Systems articles

Displaying 1 - 20 of 394

AMS solution facilitates accelerated 28nm designs

The Cadence analogue/mixed-signal (AMS) IC design flow has achieved certification for UMC’s 28HPC+ process technology. With this certification, mutual Cadence and UMC customers have access to a comprehensive AMS solution for designing automotive, industrial internet of things (IoT) and artificial intelligence (AI) chips using 28HPC+ technology.
6th August 2019

Highly scalable switch silicon family designed for data centres

Highly scalable switch silicon family designed for data centres
Cadence Design Systems has announced that Innovium has adopted the Cadence Innovus Implementation System for its 16nm TERALYNX 12.8Tbps ethernet switches for data centres. The size and complexity of the highly innovative Innovium designs require high capacity, fast and accurate design tools for advanced-node design implementation.
6th August 2019

CDC signoff solution delivers 10X faster turnaround time

CDC signoff solution delivers 10X faster turnaround time
The CadenceConformal Litmus is a next-generation solution that provides constraints signoff and clock domain crossing (CDC) signoff, reducing overall design cycle times and enhancing the quality of silicon in complex system-on-chip (SoC) designs.
19th July 2019


Portable test and stimulus methodology and library delivered

Cadence Design Systems has delivered the Accellera Portable Test and Stimulus Specification (PSS) 1.0-compliant implementation of the popular Cadence Perspec System Methodology Library (SML) and methodology documentation.
17th July 2019

Digital flow tools meet chipmaker's expectations

The Cadence digital full flow has achieved certification for the Samsung Foundry 5nm Low-Power Early (5LPE) process with Extreme Ultraviolet (EUV) lithography technology. The Cadence tools have been confirmed to meet Samsung Foundry’s technology requirements.
3rd July 2019

DisplayPort 2.0 Verification IP accelerates SoC designs

Availability of a Verification IP (VIP) in support of the new DisplayPort 2.0 standard has been announced by Cadence Design Systems. The Cadence VIP for DisplayPort 2.0 enables designers to quickly complete the functional verification of their mobile, Audio-Visual and AR/VR system-on-chip (SoC) designs with less effort and greater assurance that the design will operate as expected.
28th June 2019

Design innovations land at Paris Air Show

Recent aerospace and defense innovations will be showcased by Cadence Design Systems at the Paris Air Show (June 17 to 20), 2019. At the event, Frank Schirrmeister, product management group director for Cadence is scheduled to deliver a workshop titled, “Systems of Systems Verification and Digital Twins for Aerospace Applications,” on Thursday, June 20 at 11 a.m. 
13th June 2019

Kazakhstan University joins Cadence Academic Network

Kazakhstan University joins Cadence Academic Network
Nazarbayev University, Kazakhstan has become the first university in Central Asia to join the Cadence Academic Network and become a Cadence Certified Lab. The certification was granted to the university after the completion of Cadence certified trainings by their teachers and examiners.  
5th June 2019

Sign off tools speed up 16 nm ASIC chip tapeout

Full-flow digital and signoff tools from Cadence were used by Socionext for the successful production tapeout of its latest large, 16nm ASIC chip and it has built a design environment for its 7nm designs. Using the capabilities of the integrated full flow, Socionext sped design closure on its 16nm design when compared with its previous solution.
5th June 2019

Cloud program can accelerate chip design projects

Cloud program can accelerate chip design projects
The launch of Cadence Design Systems Cloud Passport Partner Program aims to give customers a proven and easier path to the cloud when their internal IT teams desire assistance. Cadence has engaged with program members to ensure they are knowledgeable and proficient at deploying Cadence tools in cloud-based electronic design environments.
3rd June 2019

Circuit simulator delivers 10X performance gains

The Spectre X Simulator from Cadence Design Systems is a massively parallel circuit simulator designed to provide up to 10X performance gains, while maintaining accuracy in analogue, mixed-signal and RF applications. The simulator can solve 5X larger designs when compared to previous simulation solutions, enabling customers to effectively simulate circuits containing millions of transistors and billions of parasitics in a post-layout verification flow.
3rd June 2019

Prototyping system scales to multi-MHz performance for billion gate designs

Prototyping system scales to multi-MHz performance for billion gate designs
Verification Suite and System Innovation offerings have been expanded at Cadence Design Systems with the announcement of the Protium X1 Enterprise Prototyping Platform, a data centre-optimised FPGA-based prototyping system providing multi-MHz speed for early software development, hardware/software regressions and full system validation.
29th May 2019

Enterprise prototyping system for early software development

Enterprise prototyping system for early software development
It has been announced that Cadence Design Systems has expanded its Verification Suite and System Innovation offerings with the Cadence Protium X1 Enterprise Prototyping Platform, the first data centre-optimised FPGA-based prototyping system providing multi-MHz speed for early software development, hardware/software regressions and full system validation.
29th May 2019

7nm RAK supports high-performance CPUs

Full-flow digital and signoff tools from Cadence Design Systems now support the new high-performance, high-efficiency Arm Cortex-A77 CPU for next-generation smartphones, laptops, and other mobile devices. To accelerate the adoption of Arm’s latest processor, Cadence delivered a complete 7nm Rapid Adoption Kit (RAK) that utilises Arm 7nm POP IP libraries.
28th May 2019

Verification suite chosen to accelerate product development

The full Cadence Verification Suite has been deployed by Thinci to accelerate the design and verification of its machine learning and artificial intelligence (AI) system-on-chip (SoC) designs. The Cadence Verification Suite provides Thinci access to new technologies and methodologies to achieve faster verification and design closure, shortening the product development schedule by months while improving simulation speed.
24th May 2019

Platforms offer route to first-pass silicon success

Innovium has adopted Cadence Design Systems’ Palladium Z1 Enterprise Emulation Platform and Protium S1 FPGA-Based Prototyping Platform to achieve first-pass silicon success on its high-performance, scalable, production-ready TERALYNX ethernet switch for the data centre.
19th May 2019

DSP/IP Core pursues grand SLAM

DSP/IP Core pursues grand SLAM
Targeting the automotive, AR/VR, drone, mobile, robotics and surveillance markets, Cadence Design Systems has expanded the high end of its Tensilica Vision DSP product family with the introduction of the Vision Q7 DSP delivering up to 1.82 tera operations per second (TOPS).
15th May 2019

Verification platform delivers 2X design compilation capacity

Verification platform delivers 2X design compilation capacity
The verification market is growing as it represents more and more of the costs of chip design, and as processes move deeper into sub-micron territory, costs could be up to 80% for designers using 5nm nodes. To meet this challenge Cadence Design Systems has unveiled the third generation of its Jasper Gold Formal Verification Platform, featuring machine learning technology and core formal technology enhancements.
8th May 2019

Design tools certified for 3D chip stacking technology

Design tools certified for 3D chip stacking technology
TSMC has certified Cadence Design System’s design solutions for the new TSMC System-on-Integrated-Chips (TSMC-SoIC) 3D advanced chip stacking technology, which integrates heterogenous chips—including logic ICs and memory—that are fabricated on different process nodes onto a single chip stack for a subsequent packaging process.
24th April 2019

Memory IP subsystem wins ISO 26262 ASIL C certification

Good news for Cadence Design Systems is that its LPDDR4/4X memory IP subsystem, utilising TSMC’s 16nm FinFET Compact (16FFC) technology, has achieved ISO 26262 ASIL C certification from SGS-TÜV Saar. The certification confirms that the Cadence IP is complete and ready for use by customers creating advanced systems-on-chip (SoCs) for advanced driver assistance systems (ADAS) and L3/L4 autonomous driving applications.
23rd April 2019


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EMO Hannover 2019
16th September 2019
Germany Hannover
European Microwave Week 2019
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France Porte De Versailles Paris
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New Scientist Live 2019
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