Cadence Design Systems

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Phone: +44.1344.360333

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Web: www.cadence.com


Cadence Design Systems articles

Displaying 1 - 20 of 400

Integrated power integrity solution enables signoff at 7nm

A comprehensive static timing/signal integrity analysis and power integrity analysis tool, which enables engineers to create reliable designs at 7nm and below has been released by Cadence Design Systems. The Tempus Power Integrity Solution is the result of an integration between the Cadence Tempus Timing Signoff Solution and the Voltus IC Power Integrity Solution.
6th November 2019

Cadence corrals four partner awards from TSMC

Cadence corrals four partner awards from TSMC
Cadence Design Systems was presented with four TSMC Partner of the Year awards at the TSMC 2019 Open Innovation Platform (OIP) Ecosystem Forum. Cadence achieved recognition for the joint development of the N6 design infrastructure, SoIC design solution, cloud-based productivity solution and DSP IP.
30th October 2019

VIP for NVMe 1.4 eases path to SoC verification

What is said to be the industry’s first Verification IP (VIP) in support of the new NVM Express 1.4 (NVMe) protocol has been released by Cadence Design Systems. The Cadence VIP for NVMe 1.4 enables designers to quickly and thoroughly verify their storage, data centre and high-performance computing (HPC) system-on-chip (SoC) designs with less effort and a greater assurance that the SoC will meet the protocol standards.
25th October 2019


Cadence, Arm and Samsung deliver 5LPE Flow for “Hercules” CPU

Cadence Design Systems has collaborated with Samsung Foundry and Arm to deliver a complete, high-performance digital implementation and signoff full flow for the rapid implementation of the next-generation Arm “Hercules” CPU using the Samsung Foundry 5nm Low-Power Early (5LPE) process technology.
9th October 2019

Cadence design tools get thumbs-up from TSMC

Digital and signoff full flow and custom/analogue tools from Cadence Design Systems have achieved certification on TSMC’s N6 and N5/N5P process technologies. The Cadence tools have attained the latest N6 and N5/N5P Design Rule Manual (DRM) and SPICE certification, advancing next-generation mobile application development.
25th September 2019

Co-simulation solution meets electrical-thermal challenges

Co-simulation solution meets electrical-thermal challenges
The system analysis and design market has a new solution with the introduction of the Cadence CelsiusThermal Solver, a complete electrical-thermal co-simulation solution for the full hierarchy of electronic systems from ICs to physical enclosures. Following the launch of the Clarity 3D Solver earlier this year, the Celsius Thermal Solver is the second innovative product in Cadence’s new system analysis initiative.
16th September 2019

AMS solution facilitates accelerated 28nm designs

The Cadence analogue/mixed-signal (AMS) IC design flow has achieved certification for UMC’s 28HPC+ process technology. With this certification, mutual Cadence and UMC customers have access to a comprehensive AMS solution for designing automotive, industrial internet of things (IoT) and artificial intelligence (AI) chips using 28HPC+ technology.
6th August 2019

Highly scalable switch silicon family designed for data centres

Highly scalable switch silicon family designed for data centres
Cadence Design Systems has announced that Innovium has adopted the Cadence Innovus Implementation System for its 16nm TERALYNX 12.8Tbps ethernet switches for data centres. The size and complexity of the highly innovative Innovium designs require high capacity, fast and accurate design tools for advanced-node design implementation.
6th August 2019

CDC signoff solution delivers 10X faster turnaround time

CDC signoff solution delivers 10X faster turnaround time
The CadenceConformal Litmus is a next-generation solution that provides constraints signoff and clock domain crossing (CDC) signoff, reducing overall design cycle times and enhancing the quality of silicon in complex system-on-chip (SoC) designs.
19th July 2019

Portable test and stimulus methodology and library delivered

Cadence Design Systems has delivered the Accellera Portable Test and Stimulus Specification (PSS) 1.0-compliant implementation of the popular Cadence Perspec System Methodology Library (SML) and methodology documentation.
17th July 2019

Digital flow tools meet chipmaker's expectations

The Cadence digital full flow has achieved certification for the Samsung Foundry 5nm Low-Power Early (5LPE) process with Extreme Ultraviolet (EUV) lithography technology. The Cadence tools have been confirmed to meet Samsung Foundry’s technology requirements.
3rd July 2019

DisplayPort 2.0 Verification IP accelerates SoC designs

Availability of a Verification IP (VIP) in support of the new DisplayPort 2.0 standard has been announced by Cadence Design Systems. The Cadence VIP for DisplayPort 2.0 enables designers to quickly complete the functional verification of their mobile, Audio-Visual and AR/VR system-on-chip (SoC) designs with less effort and greater assurance that the design will operate as expected.
28th June 2019

Design innovations land at Paris Air Show

Recent aerospace and defense innovations will be showcased by Cadence Design Systems at the Paris Air Show (June 17 to 20), 2019. At the event, Frank Schirrmeister, product management group director for Cadence is scheduled to deliver a workshop titled, “Systems of Systems Verification and Digital Twins for Aerospace Applications,” on Thursday, June 20 at 11 a.m. 
13th June 2019

Kazakhstan University joins Cadence Academic Network

Kazakhstan University joins Cadence Academic Network
Nazarbayev University, Kazakhstan has become the first university in Central Asia to join the Cadence Academic Network and become a Cadence Certified Lab. The certification was granted to the university after the completion of Cadence certified trainings by their teachers and examiners.  
5th June 2019

Sign off tools speed up 16 nm ASIC chip tapeout

Full-flow digital and signoff tools from Cadence were used by Socionext for the successful production tapeout of its latest large, 16nm ASIC chip and it has built a design environment for its 7nm designs. Using the capabilities of the integrated full flow, Socionext sped design closure on its 16nm design when compared with its previous solution.
5th June 2019

Cloud program can accelerate chip design projects

Cloud program can accelerate chip design projects
The launch of Cadence Design Systems Cloud Passport Partner Program aims to give customers a proven and easier path to the cloud when their internal IT teams desire assistance. Cadence has engaged with program members to ensure they are knowledgeable and proficient at deploying Cadence tools in cloud-based electronic design environments.
3rd June 2019

Circuit simulator delivers 10X performance gains

The Spectre X Simulator from Cadence Design Systems is a massively parallel circuit simulator designed to provide up to 10X performance gains, while maintaining accuracy in analogue, mixed-signal and RF applications. The simulator can solve 5X larger designs when compared to previous simulation solutions, enabling customers to effectively simulate circuits containing millions of transistors and billions of parasitics in a post-layout verification flow.
3rd June 2019

Prototyping system scales to multi-MHz performance for billion gate designs

Prototyping system scales to multi-MHz performance for billion gate designs
Verification Suite and System Innovation offerings have been expanded at Cadence Design Systems with the announcement of the Protium X1 Enterprise Prototyping Platform, a data centre-optimised FPGA-based prototyping system providing multi-MHz speed for early software development, hardware/software regressions and full system validation.
29th May 2019

Enterprise prototyping system for early software development

Enterprise prototyping system for early software development
It has been announced that Cadence Design Systems has expanded its Verification Suite and System Innovation offerings with the Cadence Protium X1 Enterprise Prototyping Platform, the first data centre-optimised FPGA-based prototyping system providing multi-MHz speed for early software development, hardware/software regressions and full system validation.
29th May 2019

7nm RAK supports high-performance CPUs

Full-flow digital and signoff tools from Cadence Design Systems now support the new high-performance, high-efficiency Arm Cortex-A77 CPU for next-generation smartphones, laptops, and other mobile devices. To accelerate the adoption of Arm’s latest processor, Cadence delivered a complete 7nm Rapid Adoption Kit (RAK) that utilises Arm 7nm POP IP libraries.
28th May 2019


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