Cadence has announced that the 112G-LR SerDes is silicon proven on the HBM3/GLink/CoWoS platform from Global Unichip Corp. (GUC).

Cadence has announced that it has collaborated with TSMC for the Cadence Virtuoso platform for the 79GHz mmWave design reference flow on TSMC’s N16 process.

Cadence Design Systems has announced the tapeout of Cadence 16G UCIe 2.5D advanced package IP on TSMC’s 3nm (N3E) process technology.

Cadence has announced the new Cadence Virtuoso Studio, a next-gen custom design platform that delivers an optimal design experience and ushers in the future for custom analogue design.

Cadence Design Systems announced the Cadence EMX Designer, a passive device synthesis and optimisation technology that delivers, in split seconds, design rule check (DRC)-clean parametric cells (PCells) and accurate electromagnetic (EM) models of passive devices, such as inductors, transformers and T-coils.

Cadence Design Systems has announced that it has demonstrated interoperability between the silicon-proven Cadence LPDDR5X memory interface IP and SK hynix’s LPDDR5T (Turbo) mobile DRAM, operating at speeds in excess of the LPDDR5X standard.

Cadence Design Systems has announced the Cadence Allegro X AI technology, a next-generation system design technology that offers revolutionary improvements in performance and automation.

Cadence has announced that it is making a $50 million purpose-driven investment in an impact investment program managed by RBC Global Asset Management (RBC GAM) to address racial wealth inequities in affordable housing, homeownership and small business.

Cadence Design Systems has announced the availability of 13 new Verification IP (VIP) solutions that enable engineers to quickly and effectively verify their designs to meet the specifications for the latest standards protocols.

Using Innovus Implementation, GUC delivered a 3.16GHz HPC core design with 3.5M instances on the TSMC N3 process technology. GUC realised a 9% area shrink and an 8% reduction in power consumption on a CPU design on the TSMC N5 process using the AI-enabled Cadence Cerebrus.

Cadence announced the LPDDR5X memory interface IP design optimsed to operate at 8533Mbps—up to 33% faster than the previous generation of LPDDR IP.

Cadence has announced that Cadence Tensilica HiFi DSP IP supports Dolby Atmos for cars making it the first DSP IP with this capability.

Cadence Design Systems, a collaborative partner in the Samsung Advanced Foundry Ecosystem (SAFE), has announced that it has expanded its collaboration with Samsung Foundry to accelerate 3D-IC (three-dimension integrated circuit) design.

Cadence Design Systems has announced the Cadence Certus Closure Solution to address growing chip-level design size and complexity challenges.

Cadence Design Systems has announced that the Cadence Voltus-XFi Custom Power Integrity solution is optimised and certified for use with Samsung Foundry’s advanced 5LPE process technology.

Cadence Design Systems announces that Samsung Foundry has certified an 8nm RFIC design reference flow to develop 5G RFICs for use with sub-6GHz to millimeter wave (mmWave) applications.

Mick Elliott, Editor at Electronic Specifier, visited the Cadence Design Systems stand at European Microwave Week where Senior Product Marketing Manager David Vye described the latest developments in RF and microwave design tools.

Cadence Design Systems has announced the delivery of the Cadence Joint Enterprise Data and AI (JedAI) Platform.

Cadence Design Systems has announced that Arm is leveraging Cadence Liberate MX Trio Characterization to enhance the quality of its embedded memory instances and compilers and speed time to market.

Cadence Design Systems has announced that Samsung Foundry has deployed the Cadence Spectre FX Simulator for FastSPICE-based verification of their large-scale analogue and mixed-signal IP on 3nm, 4nm and 5nm processes.