Cadence Design Systems

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Web: www.cadence.com


Cadence Design Systems articles

Displaying 1 - 20 of 388

Design innovations land at Paris Air Show

Recent aerospace and defense innovations will be showcased by Cadence Design Systems at the Paris Air Show (June 17 to 20), 2019. At the event, Frank Schirrmeister, product management group director for Cadence is scheduled to deliver a workshop titled, “Systems of Systems Verification and Digital Twins for Aerospace Applications,” on Thursday, June 20 at 11 a.m. 
13th June 2019

Kazakhstan University joins Cadence Academic Network

Kazakhstan University joins Cadence Academic Network
Nazarbayev University, Kazakhstan has become the first university in Central Asia to join the Cadence Academic Network and become a Cadence Certified Lab. The certification was granted to the university after the completion of Cadence certified trainings by their teachers and examiners.  
5th June 2019

Sign off tools speed up 16 nm ASIC chip tapeout

Full-flow digital and signoff tools from Cadence were used by Socionext for the successful production tapeout of its latest large, 16nm ASIC chip and it has built a design environment for its 7nm designs. Using the capabilities of the integrated full flow, Socionext sped design closure on its 16nm design when compared with its previous solution.
5th June 2019


Cloud program can accelerate chip design projects

Cloud program can accelerate chip design projects
The launch of Cadence Design Systems Cloud Passport Partner Program aims to give customers a proven and easier path to the cloud when their internal IT teams desire assistance. Cadence has engaged with program members to ensure they are knowledgeable and proficient at deploying Cadence tools in cloud-based electronic design environments.
3rd June 2019

Circuit simulator delivers 10X performance gains

The Spectre X Simulator from Cadence Design Systems is a massively parallel circuit simulator designed to provide up to 10X performance gains, while maintaining accuracy in analogue, mixed-signal and RF applications. The simulator can solve 5X larger designs when compared to previous simulation solutions, enabling customers to effectively simulate circuits containing millions of transistors and billions of parasitics in a post-layout verification flow.
3rd June 2019

Prototyping system scales to multi-MHz performance for billion gate designs

Prototyping system scales to multi-MHz performance for billion gate designs
Verification Suite and System Innovation offerings have been expanded at Cadence Design Systems with the announcement of the Protium X1 Enterprise Prototyping Platform, a data centre-optimised FPGA-based prototyping system providing multi-MHz speed for early software development, hardware/software regressions and full system validation.
29th May 2019

Enterprise prototyping system for early software development

Enterprise prototyping system for early software development
It has been announced that Cadence Design Systems has expanded its Verification Suite and System Innovation offerings with the Cadence Protium X1 Enterprise Prototyping Platform, the first data centre-optimised FPGA-based prototyping system providing multi-MHz speed for early software development, hardware/software regressions and full system validation.
29th May 2019

7nm RAK supports high-performance CPUs

Full-flow digital and signoff tools from Cadence Design Systems now support the new high-performance, high-efficiency Arm Cortex-A77 CPU for next-generation smartphones, laptops, and other mobile devices. To accelerate the adoption of Arm’s latest processor, Cadence delivered a complete 7nm Rapid Adoption Kit (RAK) that utilises Arm 7nm POP IP libraries.
28th May 2019

Verification suite chosen to accelerate product development

The full Cadence Verification Suite has been deployed by Thinci to accelerate the design and verification of its machine learning and artificial intelligence (AI) system-on-chip (SoC) designs. The Cadence Verification Suite provides Thinci access to new technologies and methodologies to achieve faster verification and design closure, shortening the product development schedule by months while improving simulation speed.
24th May 2019

Platforms offer route to first-pass silicon success

Innovium has adopted Cadence Design Systems’ Palladium Z1 Enterprise Emulation Platform and Protium S1 FPGA-Based Prototyping Platform to achieve first-pass silicon success on its high-performance, scalable, production-ready TERALYNX ethernet switch for the data centre.
19th May 2019

DSP/IP Core pursues grand SLAM

DSP/IP Core pursues grand SLAM
Targeting the automotive, AR/VR, drone, mobile, robotics and surveillance markets, Cadence Design Systems has expanded the high end of its Tensilica Vision DSP product family with the introduction of the Vision Q7 DSP delivering up to 1.82 tera operations per second (TOPS).
15th May 2019

Verification platform delivers 2X design compilation capacity

Verification platform delivers 2X design compilation capacity
The verification market is growing as it represents more and more of the costs of chip design, and as processes move deeper into sub-micron territory, costs could be up to 80% for designers using 5nm nodes. To meet this challenge Cadence Design Systems has unveiled the third generation of its Jasper Gold Formal Verification Platform, featuring machine learning technology and core formal technology enhancements.
8th May 2019

Design tools certified for 3D chip stacking technology

Design tools certified for 3D chip stacking technology
TSMC has certified Cadence Design System’s design solutions for the new TSMC System-on-Integrated-Chips (TSMC-SoIC) 3D advanced chip stacking technology, which integrates heterogenous chips—including logic ICs and memory—that are fabricated on different process nodes onto a single chip stack for a subsequent packaging process.
24th April 2019

Memory IP subsystem wins ISO 26262 ASIL C certification

Good news for Cadence Design Systems is that its LPDDR4/4X memory IP subsystem, utilising TSMC’s 16nm FinFET Compact (16FFC) technology, has achieved ISO 26262 ASIL C certification from SGS-TÜV Saar. The certification confirms that the Cadence IP is complete and ready for use by customers creating advanced systems-on-chip (SoCs) for advanced driver assistance systems (ADAS) and L3/L4 autonomous driving applications.
23rd April 2019

Parasitic extraction tools enabled for gate-all-around technology

Parasitic extraction tools enabled for gate-all-around technology
It has been announced by Cadence Design Systems that the Cadence Innovus Implementation System and Quantus Extraction Solution are now enabled for the Samsung Foundry Gate-All-Around (GAA) technology. The Cadence tools have been confirmed to meet Samsung Foundry’s technology requirements, which lets customers who produce high-end products for the mobile, networking, server and automotive markets leverage GAA technology.
4th April 2019

Verification IP for USB4 enables early adoption

Verification IP for USB4 enables early adoption
The availability of the industry’s first Verification IP (VIP) in support of the recently announced USB4 standard has been announced by Cadence Design Systems. The Cadence VIP for USB4 enables engineers to develop standard-compliant system-on-chip (SoC) designs, completing functional verification of the design with less effort and greater assurance that the SoC will operate as expected.
27th March 2019

Accelerating delivery of advanced 3D flash memory devices

Accelerating delivery of advanced 3D flash memory devices
Cadence Design Systems announced that Toshiba Memory Corporation has successfully used the Cadence CMP Process Optimiser, a model calibration and prediction tool that accurately simulates multi-layer thickness and topography variability for the entire layer stack, to accelerate the delivery of its advanced 3D flash memory devices. With the Cadence solution in place, Toshiba Memory Corporation achieved 95.7% accuracy to silicon.
18th March 2019

LPDDR5 IP solution targets AI, IoT applications

Early availability of the complete, silicon-proven Cadence Denali Gen2 IP for LPDDR5/4/4X in TSMC’s 7nm FinFET process technology has been announced by Cadence Design Systems. Offering up to 1.5X faster bandwidth than the fastest speed of LPDDR4 and LPDDR4X, the LPDDR5 standard enables high bandwidth with low power consumption, making it well suited for mobile computing, AI, IoT, cryptocurrency mining and automotive applications.
8th March 2019

embedded world: DSP lifts radar/lidar and 5G performance

embedded world: DSP lifts radar/lidar and 5G performance
Boosting performance by up to 10X for Automotive Radar/Lidar and up to 30X for 5G communications the Cadence Tensilica ConnX B20 DSP IP becomes the highest-performing DSP in the ConnX family. Based on a deeper processor pipeline architecture, this DSP provides a faster and more power-efficient solution for the automotive and 5G communications markets, including next-generation radar, lidar, vehicle-to-everything (V2X), user equipment (UE)/infrastructure and IoT applications.
26th February 2019

EDA tool vendor selected for advanced node chip design

EDA tool vendor selected for advanced node chip design
It has been announced that GLOBALFOUNDRIES (GF), has chosen Cadence Design Systems as the primary EDA tool vendor for use in Avera Semi, a GF subsidiary, for advanced node chip design projects. The Avera Semi engineering team has reportedly come to rely on the features, capacity, speed and scalability of the Cadence digital and signoff, system and verification, custom IC and PCB design and analysis tools and flows.
18th February 2019


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