Claiming to have achieved the highest known performance in the industry, Cadence have announced that their DDR4 PHY IP for 28nm delivered 2667Mbps performance. The DDR4 PHY IP is a silicon-proven, robust and low-risk DDR PHY that has been verified with the Cadence DDR4 controller IP.

Renesas have announced that, through using Cadence C-to-Silicon Compiler, that they have been able to shorten HEVC IP design and verification time by 70%. This enabled the company to quickly offer their customers IP supporting this next-generation video codec.

Licensing the full suite of MPEG AAC codecs from Fraunhofer IIS for use with the Tensilica HiFi DSP, Cadence Design Systems plans to use the products to enhance the library of over 100 audio/voice software packages optimised for the HiFi DSP family. New standards include the AAC-ELD communication codec, which enables telephone conversations with the highest possible audio quality, and xHE-AAC, which is the latest upgrade to the MPEG AAC family of...

The new Encounter RTL Compiler version 13.1 from Cadence now includes a new suite of physically aware RTL synthesis capabilities. This new suite of physically aware RTL synthesis capabilities enables 15 percent improvement in power, performance and area on today’s most complex advanced node chip designs that face timing or congestion challenges. The new capabilities enable engineers to use physical aware techniques at the earliest phases o...

Cadence Design Systems has announced a new power signoff solution which delivers record performance and capacity power analysis. Meeting the needs of next-generation chip design, Voltus IC Power Integrity Solution is integrated with Cadence IC, package, PCB and system tools. This integration allows designers to better manage power issues throughout the product development cycle and achieve up to 10 times faster power signoff.

Cadence Design Systems introduce the new Cadence Interconnect Workbench, a software solution providing cycle-accurate performance analysis of interconnects throughout the system-on-chip design process. Quickly identifying design issues under critical traffic condition, Interconnect Workbench enables users to improve device performance and reduce time to market. Working with Cadence Interconnect Validator, Interconnect Workbench offers a complete ...

At CDNLive India 2013, Cadence Design Systems, Inc today introduced Spectre XPS (eXtensive Partitioning Simulator), a high-performance FastSPICE simulator that enables faster and more comprehensive simulation for large, complex chip designs. The new simulator delivers ground-breaking partitioning technology that brings up to 10X faster throughput compared to competitive offerings, shortening simulation from weeks to days.  Spectre XPS unique...

Cadence Design Systems is the first IP core supplier to offer DTS Neural Surround Support. DTS Neural Surround, combined with the Cadence Tensilica HiFi Audio/Voice DSPs, brings a home theater-like experience to automobiles and A/V receivers. This significantly enhances the sound quality of upmixing from compressed media file types such as MP3.

Cadence Design Systems, Inc today received three TSMC Partner of the Year Awards during TSMC’s Open Innovation Platform forum – accepting the most awards from the event. Cadence was presented awards for three different categories including awards for analog/mixed signal IP, 16nm FinFET design infrastructure, and 3D-IC design solutions.  The awards underscore the deep collaboration between the two companies in bringing the highest...

Cadence Design Systems has introduced its Secure Digital 4.0 Host Controller Intellectual Property core, which allows designers to achieve the maximum memory card access performance of up to 312MB/s. This is 3 times the performance of the previous specification. The Cadence SD 4.0 Host Controller IP core is compliant with SD Specification Version 4.0 by the SD Association and is the fastest IP solution on the market.

In a move to further reduce time to market for both semiconductor and system manufacturers, Cadence Design Systems Inc today introduced the Palladium XP II Verification Computing Platform as part of an enhanced System Development Suite, significantly speeding up hardware and software verification. The Palladium XP II platform builds on the award-winning Palladium XP emulation technology by boosting verification performance by up to 50% and extend...

In an move to further reduce time to market for both semiconductor and system manufacturers, Cadence Design Systems has today introduced the Palladium XP II Verification Computing Platform as part of an enhanced System Development Suite, significantly speeding up hardware and software verification. The Palladium XP II platform builds on the award-winning Palladium XP emulation technology by boosting verification performance by up to 50% and exten...

Cadence Design Systems reveal their second quarter of fiscal year 2013 results. Cadence reported second quarter 2013 revenue of $362 million, compared to revenue of $326 million reported for the same period in 2012. On a GAAP basis, Cadence recognized net income of $9 million, or $0.03 per share on a diluted basis, in the second quarter of 2013, compared to net income of $36 million, or $0.13 per share on a diluted basis, in the same period in 20...

Cadence Design Systems reveal that after extensive benchmark testing, semiconductor foundry United Microelectronics Corporation has adopted the Cadence “in-design” and signoff design-for-manufacturing flows to perform physical signoff and electrical variability optimization for 28nm designs. The flows address both random and systematic yield issues, providing customers with another proven foundry flow for 28nm designs.

Cadence Design Systems reveal that Hitachi decreased development time and accelerated time to market for new IT products by utilizing the Cadence Rapid Prototyping Platform. Hitachi collaborated with Cadence as a strategic partner on an integrated verification and early software development environment to enhance quality and shorten turnaround time for Hitachi’s new IT products. Hitachi successfully implemented a system-level co-verification en...

Cadence unveil that Fujitsu has decreased the regression verification time for a system-on-chip design by 3X using the Incisive Enterprise Simulator and the Incisive Enterprise Manager. Part of the Cadence System Development Suite, the Incisive functional verification platform delivers unique verification management and automation capabilities that tackle the complexities of SoC verification.

Cadence Design Systems unveil that Ricoh have chosen the Cadence Palladium XP verification computing platform for its multifunction printer system-on-chip development, after an extensive competitive benchmarking process. Achieving the fastest design “bring-up” compared to alternative solutions, the Palladium XP platform with Cadence PCIe 2.0 Accelerated Verification IP also delivered a 40X verification speed-up over RTL logic simulation.

Cadence Design Systems announce a groundbreaking approach to custom design with its Virtuoso Layout Suite for Electrically Aware Design. Offering increased design team productivity and circuit performance for custom ICs, Virtuoso Layout Suite EAD allows engineers to reduce their circuit design cycle by up to 30 percent while optimizing chip size and performance.

Cadence Design Systems announced that TSMC has expanded collaboration with Cadence on the Virtuoso custom and analog design platform to design and verify its own cutting-edge IP. Additionally, TSMC has extended its native SKILL-based process design kits (PDKs) portfolio to 16 nanometers, creating and delivering fully qualified and high-quality native SKILL-based PDKs to enable all the leading-edge features of the Virtuoso platform.

Addressing the design challenge of reducing energy consumption of power-hungry datacenters and enterprise applications, Cadence Design Systems, today announced new design IP for low-power PCI Express development.