Cadence received an award for the “Analog/Mixed-Signal IP” category. The winners of the IP award are chosen based on customer feedback, TSMC9000 compliance, number of tapeouts, wafer volume and support. Cadence has a mature and broad offering of analog/mixed-signal IP including 28nm IP designs.
The award for “Joint Development of 16nm FinFET Design Infrastructure” is a validation of a long-standing relationship between Cadence and TSMC, working together on advanced node technology development and specifically FinFET enablement. The “Joint Delivery of 3D-IC Design Solution” award is in recognition of the joint collaboration on the new 3D-IC reference flow, and TSMC’s first innovative, true 3D stacking 3D-IC testchip tapeout.
“The awards Cadence received were based on the quality results that were delivered for IP, 16nm FinFET and 3D-IC solutions,” said Suk Lee, TSMC Senior Director, Design Infrastructure Marketing. “We look forward to continuing our partnership and delivering innovative design solutions to our mutual customers in the years to come.”