Cadence Receives Three TSMC Partner of the Year Awards for Design IP, 16nm FinFET and 3D-IC Solutions
Cadence Design Systems, Inc today received three TSMC Partner of the Year Awards during TSMC’s Open Innovation Platform forum – accepting the most awards from the event. Cadence was presented awards for three different categories including awards for analog/mixed signal IP, 16nm FinFET design infrastructure, and 3D-IC design solutions. The awards underscore the deep collaboration between the two companies in bringing the highest quality design capabilities to IC designers around the world.
Cadence received an award for the “Analog/Mixed-Signal IP” category. The winners of the IP award are chosen based on customer feedback, TSMC9000 compliance, number of tapeouts, wafer volume and support. Cadence has a mature and broad offering of analog/mixed-signal IP including 28nm IP designs.
The award for “Joint Development of 16nm FinFET Design Infrastructure” is a validation of a long-standing relationship between Cadence and TSMC, working together on advanced node technology development and specifically FinFET enablement. The “Joint Delivery of 3D-IC Design Solution” award is in recognition of the joint collaboration on the new 3D-IC reference flow, and TSMC’s first innovative, true 3D stacking 3D-IC testchip tapeout.
“The awards Cadence received were based on the quality results that were delivered for IP, 16nm FinFET and 3D-IC solutions,” said Suk Lee, TSMC Senior Director, Design Infrastructure Marketing. “We look forward to continuing our partnership and delivering innovative design solutions to our mutual customers in the years to come.”
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