RTL Complier expands physically aware RTL synthesis capabilities

As geometries shrink beyond 28nm, changes in interconnect characteristics make it much more difficult to achieve optimal timing and closure. The new RTL Compiler capabilities allow designers to address these challenges earlier in the design process so they can achieve faster timing closure, while improving performance, power and area.

“While collaborating with Cadence on the development of several production designs, Fujitsu deployed RTL Compiler’s next-generation physically aware RTL synthesis technologies on a 1GHz, eight-CPU core design,” said Satoru Yamaguchi, president and chief executive officer of Fujitsu Semiconductor America. “We were able to improve timing and area by more than 10 percent, allowing us to shrink the chips for our customer while demonstrating the benefit of this new synthesis solution.”

The new RTL synthesis capabilities include physically aware structuring, mapping, multi-bit cell inferencing and design for test that offer significant benefits for Cadence customers. Physically aware structuring and mapping can improve performance by more than 10 percent and area by more than 15 percent on complex SoCs by considering pin and register placement when deciding which micro-architectures to synthesize to, and how to balance them. Physically aware multi-bit cell inferencing can lower power by more than 10 percent by merging single registers into multi-bit registers that share a clock.

“Cadence has re-architected RTL Compiler to weave physical awareness into stages of RTL synthesis that were traditionally logic only, allowing engineers to leverage floorplan and placement data as early as possible in the flow to ensure correlation with the Encounter Digital Implementation System,” commented Anirudh Devgan, senior vice president of the Digital and Signoff Group at Cadence.