A solution for complete interconnect testing and validation has been released by Teledyne LeCroy. The WavePulser 40iX is a tool for high-speed hardware designers and test engineers to characterise and analyse interconnects and cables for high-speed serial protocols such as PCI Express, HDMI, USB, SAS, SATA, Fibre Channel, InfiniBand, Gigabit Ethernet, and Automotive Ethernet.
Until now, interconnect testing and validation has been bifurcated between time- and frequency-domain testing.
For the former, signal-integrity engineers have used TDRs to characterise step/impulse response by generating an impedance profile. TDRs are characterised by high spatial resolution, enabling precise location of impairments along the transmission line, noted by changes in the impedance profile.
For the latter, VNAs, characterised by high dynamic range, are typically used by microwave engineers to measure S-parameters of radio-frequency (RF) components.
When adapted to high-speed interconnect testing, VNAs suffer from the need to extrapolate response to DC and from sub-par analysis tools for time-domain simulation, emulation, time gating, and jitter analysis. Neither test instrument fully meets the needs of design engineers who test and validate high-speed interconnects.
The WavePulser 40iX greatly simplifies the process of high-speed interconnect testing and validation by unifying time- and frequency-domain characterisations. The WavePulser 40iX, in a single acquisition and in one instrument, performs complete S-parameter frequency characterisation like a vector network analyser (VNA), impedance profiling like a time-domain reflectometer (TDR), and also delivers deep analysis capabilities.
Quick to calibrate automatically and easy to use, the WavePulser 40iX unravels the complexities of the physical signal path, accurately characterising serial data cables, channels, connectors, vias, backplanes, printed-circuit boards, chip and SoC packages, and more.
The measured S-parameters also may be used for additional analyses, including time gating, de-embedding of interconnects, eye diagrams, optimised equalisation settings, serial-data pattern simulation, and advanced jitter analysis with breakdown into component elements.