Designing proper circuit protection for wearables

18th February 2015
Nat Bowers

As consumers become increasingly dependent on wearables, circuit designers are tasked with incorporating advanced circuit protection technologies that safeguard the device as well as the user. Without proper protection, the device’s sensor circuits, battery-charging interfaces, buttons or data I/Os could be irreparably damaged by ESD that is often caused by close interaction with the user.

By James Colby, Business & Technology Development Manager, Semiconductor Business Unit, Littelfuse.

Wearable computing is one of the hottest consumer electronics trends on the market. Have you attended an electronics or design tradeshow lately? Have you visited a big box retailer or browsed an online electronics vendor? If so, you’ve probably seen many examples of wearable technology, including smart glasses, clothing, wristwear, footwear, neckwear and headbands. Circuit designers face many challenges in the design process stemming from the shrinking form factor of most wearables and the demand for improved device performance. This article features answers to 15 important and frequently asked questions. The answers will help today’s circuit designers improve the performance, safety and reliability of their wearable technology designs.

Device size and form factor

1. What is the benchmark for size versus ESD robustness?

In the past, large diode structures were needed to achieve excellent ESD performance (low clamping voltage). Since wafer fabrication processes and back-end assembly capabilities have steadily improved, it is now possible to have very robust ESD protection in small form factors. For example, the general purpose 01005 TVS diode from Littelfuse can withstand 30kV contact discharge (IEC 61000-4-2). It also has a dynamic resistance value of less than 1Ω.

2. How much area shrinkage can be achieved with the latest technology in ESD?

The most common discrete form factor for TVS diodes is the SOD882 package, which is equivalent to an outline of 1.0x0.6mm. Moving to the 0201 form factor (0.6x0.3mm) allows the designer to save approximately 70% in board area. Moving to the 01005 outline yields a savings of over 85% compared to the SOD882.

3. What are the downsides of a small form factor? Is there a compromise required in terms of the performance to accommodate the small form factor?

Per the advancements discussed in the first question, we are not seeing any downsides related to ESD performance. Discrete semiconductors with a small form factor can have the same level of ESD robustness (30kV) and low clamping performance (dynamic resistance of less than 1Ω) as their larger counterparts (e.g., SOD323, SOD123). However, the small size of the component may present manufacturing challenges. At 0.4x0.2mm, the 01005 package will require well-designed board treatments (solder pads, stencil thickness, etc.) to ensure that the component does not slide or 'tombstone' during the reflow solder process.

TVS diodes and ESD disruptive discharge

4. If I have discrete TVS diodes on each of the pins of the IC, will they occupy more of the board area and also cause the BOM to increase?

In general, most designs do not require board-level TVS diodes at each of the IC's pins. Instead, the designer should determine which pins have exposure to the outside of the application. Typical circuits include USB, audio, button/switch control and other data buses. Since adding these discrete devices will take up board space, it’s important to concentrate on reducing their size. In fact, we're now down to 0201 and 01005 outlines. For some applications, there are some space-saving multi-channel arrays available.

5. When IC designers create products that employ lower working voltages, can the end application (e.g. smartphone or tablet) still be reliable?

ESD protection device manufacturers continue to work to develop products with ever-lower clamping voltages. Companies like Littelfuse also work with board-level designers to ensure that proper circuit layout practices are followed to protect the reliability of the application. Coupling products with low dynamic resistance and proper board layout practices will ensure that applications with even the most sensitive IC will still perform reliably.

6. How do I choose between unidirectional or bidirectional TVS diodes?

Unidirectional diodes are typically used for DC circuits, including pushbuttons and switches. They are also designed for use in digital circuits where there is no negative voltage as part of the signal (e.g. USB, HDMI, etc.). Bidirectional diodes are used in AC circuits, which may include any signal with a negative component greater than -0.7V. Examples of these circuits include audio, analog video, legacy data ports (e.g. CAN, LIN, RS-485, etc.) and RF interfaces (e.g. cellular, Bluetooth, NFC, etc.).

7. To protect the IC’s pins with a TVS diode, what are the key considerations for trace (from I/O, to ground)?

Unlike lightning transients, ESD does not unleash a large amount of current for a long duration. Instead, it is important to move the ESD charge from the protected circuit to the ESD reference in a very short amount of time (less than 200ns). The length of the trace (from the I/O line to the ESD component; from the ESD component to ground), not the width of the trace to the ground, is the overriding factor. This length should be kept as short as possible to limit parasitic inductance. Because of this, recent package developments include µDFN outlines that fit directly over the data lanes to eliminate the need for stub traces.

8. The length of the ground path influences the parasitic inductance, while the width influences the parasitic capacitance. In terms of form factor, how do I avoid ESD disruptive discharge?

The inductance will act as a choke for the ESD transient and degrade the protection performance. The parasitic capacitance will degrade high-speed signal performance. Designers should not only minimise the length/width of the stub trace, but also attempt to eliminate it. For the connection to the data or signal line, place the solder pad right on or adjacent to the trace, if possible. This can be done for discrete diodes as well as a number of arrays that are designed to be placed right over the data tracks. This underscores the need to consider the board-level ESD protection approach as early as possible in the design process.

9. What are the levels of Human Body Model (HBM) or Charged Device Model (CDM) for these TVS diodes? How do I determine the ideal HBM for a particular wearable technology?

Answer: HBM and CDM are designations for the ESD robustness of the ICs that run the application, including the processor, memory and ASIC. They are not designations for system-level ESD robustness or immunity. In general, applications like smartphones and PCs are characterised to the IEC 61000-4-2 standard. As a system-level specification, it allows the designer to determine whether the ESD device has the robustness and clamping capability needed to survive the system-level transient and protect the system. For board-level ESD devices, the designer can determine their robustness by reviewing the IEC 61000-4-2 rating (8, 12, 15kV contact, etc.). In addition, review the dynamic resistance value (1, 0.5Ω, etc.) to determine the level of protection provided by the devices. For wearable technology, a high IEC rating and low dynamic resistance are especially important.

Low capacitance vs. performance

10. Based on the connection between capacitance, signal integrity and ESD clamping voltage, does low capacitance affect performance?

Since significant advancements have been made regarding capacitance and ESD performance, there is no longer a tradeoff between these two characteristics. For example, new wafer fabrication processes allow the designer to create a protection device with 0.5pF of capacitance (or lower) and still have less than 1Ω of dynamic resistance. So, these low-capacitance diodes do not store any charge or impact high-speed signal integrity. The low dynamic resistance value ensures that they also have a low clamping voltage.

Some application designers consider polymeric devices and zener diodes as viable alternatives to the semiconductor ESD solutions we have discussed. However, it is important to recognise that all these options have very different characteristics, including dynamic resistance. For chipsets with robust on-chip protection (per HBM) or that were made on old processes (e.g. 130nm), polymers and zener diodes provide sufficient protection. In contrast, modern ICs made on very dense topologies (e.g. 45 and 22nm) are very sensitive to ESD pulses and require the lower dynamic resistance associated with semiconductor TVS diodes. It is vital that the circuit protection solution matches the needs of the IC that requires protection.

Early ESD planning vs. late-stage protection

11. What is one of the most challenging aspects of protecting new applications?

The biggest challenge is convincing circuit designers that circuit protection is important from the beginning of the design process. Because circuit protection devices do not add perceived value to the customer’s product or enhance the capabilities of the application, they are typically ignored until the end of the process when it’s time for EMC testing. It’s very important for designers to understand that board-level ESD protection ensures that these innovative devices are able to deliver safe, reliable performance throughout their intended operating life.

12. Why is it so important to incorporate circuit protection in the design and planning phase?

Circuit designers should consider ESD protection early in the design phase so that they can choose the ideal protection device and select the optimal layout/location before their options become limited by other components, including transformers, common mode chokes and passives.

13. Instead of implementing circuit protection early in the design process, is it possible to leave a few 0805 or 0603 package footprints at strategic places in the design?

If the designer doesn’t have enough time to do a complete ESD protection analysis during the early phase of the board layout, it should be possible to place sockets at each I/O or location where ESD is expected to enter the application. Due to the limited board space, consider choosing a 0402 or 0201 package. Because these footprints are quite common, parts can be readily sourced from several suppliers.

14. To eliminate EMI, could I incorporate ESD protection at a later stage in the design process using ferrite beads, decoupling caps or zener diodes?

Fortunately, there are multiple solutions available for protecting against ESD. To find the best solution for a specific application, it’s vital to consider the circuit’s characteristics, cost and board implementation.

Consider the example of using ferrite beads. While a ferrite bead can be an effective ESD solution for low-speed circuits, it is not appropriate for high-speed circuits like USB 2.0, USB 3.0, HDMI, etc. For these circuits, the inductance that will remediate the ESD pulse will also cause signal integrity issues. It would be better to use a low capacitance TVS diode or diode array (less than 1pF) in parallel with the data line to shunt the ESD transient away from the IC. This solution is ideal since the low capacitance will not interfere with the data signal transfer, while the clamping action of the TVS diode/diode array protects the IC.

Solutions like zener diodes will clamp an ESD event. However, they are optimised for voltage regulation, not TVS. Because of this, their dynamic resistance and clamping voltage are higher than that of TVS diodes and diode arrays. Another shortcoming is that they won’t be able to survive a high number of ESD hits.

15. In addition to choosing the correct suppression device, what is the significance of good board layout?

Board layout is very important since space is limited and several other components will compete for real estate. For optimal performance, the ESD suppressor should be located very close to the connector (ESD entry point). If there is a stub trace that runs from the protected line to the suppressor, it should be as short as possible. This will help to minimise inductive overshoot - a condition that can damage the IC by adding excessive voltage (stress). A long stub trace will add inductance to the ESD path to ground, which will cause inductive overshoot during an ESD event. The voltage that develops during inductive overshoot is added to the natural clamping response of the ESD protection component. Because of this, the IC that is to be protected experiences a much higher voltage than expected, which could lead to IC failure. By using the recommended board layout strategies, design engineers will realise enhanced efficiency and reliability in their ESD protection circuits.

Author profile: James Colby is the business and technology development manager for the Semiconductor Business Unit at Littelfuse. His responsibilities include identifying and developing strategic growth markets as well as introducing new products into those markets. He received his BSEE from Southern Illinois University (Carbondale) and his MBA from Keller Graduate School of Management (Schaumburg). He has been with Littelfuse for over 15 years and has worked in the electronics industry for more than 23 years.

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