ISi Announces Silicon Validation of Z-RAM Technology

23rd January 2006
ES Admin
Innovative Silicon Inc. (ISi), the developer of Z-RAM™ high density memory IP, has announced that it has achieved silicon validation of Z-RAM memory arrays on 90nm SOI process technologies. The company also announced that it has validated its memory bitcell (which requires only one transistor and zero capacitors) in an additional 10 fabrication processes that include 130nm SOI, 90nm SOI, and FinFET technologies. The company expects to demonstrate working silicon in multiple 65nm processes later this quarter.
“This is a real inflection point for ISi,” stated Mark-Eric Jones, president and CEO of ISi. “The technical validation we have achieved, coupled with our recent announcement with AMD, demonstrates the value of our technology to leading semiconductor manufacturers.”

ISi’s Z-RAM technology was created to solve one of the biggest challenges for SOC designers, how to shrink die sizes when memory dominates chip area and cost. With Z-RAM IP, IC manufacturers gain the benefit of having more dense memory which in turn means their SOCs, developed on SOI, can be produced at lower cost than those on bulk CMOS silicon.

ISi validated the Z-RAM technology at two separate locations – Freescale Semiconductor’s Austin Technology & Manufacturing Center, and at a leading pureplay semiconductor foundry.

“We achieved outstanding results in these 90nm technologies,” noted Dr. Pierre Fazan, co-founder and CTO of ISi. “I am particularly excited about our Soft Error Rate (SER) data obtained on multi-megabit memory macros. This data shows our memory IP is an order of magnitude better than embedded SRAM technologies and comparable to the leading embedded DRAM technologies. This, coupled with our density and performance advantages, makes Z-RAM the ideal solution for anyone using large blocks of embedded memory.”

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