Introducing the SMC 1000 8x25G serial memory controller

The serial memory controller bridges from 8 lanes of 25G open memory interface omi to by 72 bit ddr4 3200 DRAM memory. 

The memory semantics portion of the open copy protocol as defined by the open copy consortium. The SMC 1008 by 25 GAE can dramatically improve CPU or other system on chips memory subsystem performance cost and flexibility. The SMC 1008 by 25G enables four times the memory bandwidth per CPU versus traditional DDR memory media independence and lower total solution cost. 

Let's explore how the SMC 1000 helps the CPU to achieve significantly greater memory bandwidth. Traditional parallel ddr4 DRAM channels each require upwards of 300 signal and power ground pins where omi base memory channels require approximately 75. This limits the number of DRAM channels that can be practically supported on a single device package. The SMC 1008 by 25G is most commonly mounted on a differential dual inline memory module or deed in the product. 

It provides the 8 by 25G omi to the DDM connector and by 72 bit ddr4 3200 interface to the by 4 or by a dram memory components mounted on the DDM itself. A traditional parallel attached ddr4 are dim as a 288 pin connector and has a 133 millimetre length. In the video, you can see the omi base d dims have a significantly narrower 84 piece connector and are just 85 millimetres in length. 

The SMC 1008 by 25G allows these equivalent capacity diems to have a significantly narrower interface to the connected CPU. Microchip has partnered with the industry's memory suppliers smart modular Samsung and Micron to bring these highly optimised standard D dim products to market.

For more information, watch the video below.