Embedded system design is entering a new phase of complexity. Performance expectations continue to rise, integration levels are increasing, and product lifetimes are extending at the same time as supply chains are under greater scrutiny than ever before. For many OEMs and system houses, these pressures are exposing the limits of off-the-shelf silicon and prompting a reassessment of where custom ASICs can add long-term value.
This shift is not simply about achieving higher performance or lower power. Increasingly, it reflects a need for tighter alignment between system requirements and silicon implementation, particularly in applications that combine analogue, digital, RF, and security functionality. As embedded platforms evolve, the cost of compromise at the silicon level is becoming harder to absorb elsewhere in the system.
Translating system intent into silicon
One of the enduring challenges in ASIC development is bridging the gap between high-level system intent and production-ready silicon. Mixed-signal devices, in particular, demand early architectural clarity: analog performance targets, RF coexistence, digital processing requirements, test strategy, and qualification constraints are all interdependent.
When these considerations are addressed in isolation, risk accumulates quickly. By contrast, a system-led approach to ASIC development – where architecture, design, verification, and manufacturing considerations are treated as a continuous flow – allows complexity to be managed rather than deferred. This system-led approach reflects how EnSilica works with customers to translate complex requirements into production-ready custom silicon.
Recent ASIC programmes across industrial, automotive, and communications markets illustrate how early architectural decisions influence not only performance and power, but also yield, test coverage, and long-term availability. As many applications remain on mature process nodes for longevity and reliability reasons, design expertise, and proven IP often matter more than access to the latest geometry.
Manufacturing considerations move upstream
Supply resilience has become a defining concern for embedded product teams, and it is now influencing technical decisions much earlier in the design cycle. Component longevity, qualification pathways, and manufacturing continuity are all shaping how ASICs are specified and delivered.
This has placed renewed emphasis on close coordination between design and manufacturing. Understanding how architectural choices affect test complexity, ramp-up risk, and production timelines can significantly reduce friction as devices move from prototype to volume. In practice, this depends on treating manufacturing considerations as an integral part of the design process, rather than a downstream handover.
For European OEMs, there is also growing interest in maintaining strong regional design capability while ensuring access to global manufacturing ecosystems. This balance supports both technical resilience and long-term roadmap confidence, particularly in regulated or safety-critical sectors, supported in EnSilica’s case by the recent expansion of its European design footprint to include a Budapest-based team.
Security designed into the silicon
Security expectations for embedded devices continue to rise, driven by increased connectivity and more sophisticated attack surfaces. In response, the industry is moving beyond software-centric approaches towards hardware-enforced security mechanisms.
Techniques such as hardware root-of-trust, secure boot, and isolation domains are becoming baseline requirements in many applications. Emerging processor architectures that enforce memory safety in hardware – such as CHERI – are gaining attention as a way to address entire classes of vulnerabilities at source. In parallel, support for post-quantum cryptography (PQC) and alignment with recognised security frameworks such as PSA Certified are becoming increasingly important in ensuring long-term cryptographic resilience and structured hardware-rooted security implementation.
These approaches place new demands on ASIC architecture and verification, but they also offer a more robust foundation for long-lived embedded platforms. Experience designing security-aware ASICs shows these requirements are most effectively addressed when considered from the earliest system architecture stage.
Targeted intelligence at the Edge
AI is another influence on ASIC requirements, though its role in embedded systems is often more selective than headline trends suggest. Many applications benefit not from general-purpose acceleration, but from tightly optimised intelligence close to the sensor – enabling functions such as anomaly detection, predictive maintenance, or sensor fusion within strict power and latency budgets.
Custom ASICs allow these capabilities to be implemented in a way that aligns precisely with system constraints, avoiding unnecessary complexity while delivering deterministic behaviour. As Edge intelligence matures, this targeted approach is likely to become more common.
Custom silicon as a strategic tool
Taken together, these trends point to a broader re-evaluation of the role of custom ASICs. As differentiation moves deeper into the platform, silicon is increasingly viewed as a strategic asset – one that influences performance, security, cost, and supply resilience over the entire product lifecycle. A system-aware, end-to-end approach to ASIC development enables that asset to be realised with greater confidence.
Visit EnSilica at embedded world: Stand 4-559
This article originally appeared in the March’26 magazine issue of Electronic Specifier Design – see ES’s Magazine Archives for more featured publications.
