Rambus Delivers 112G XSR/USR PHY for chiplets
Rambus has expanded its portfolio of high-speed interface IP on TSMC’s 7nm process with the addition of its silicon-demonstrated 112G XSR/USR PHY. Offering unmatched power and area efficiency for next-generation applications, the 112G XSR/USR PHY is a critical enabler of chiplet and CPO architectures for data centre, networking, 5G, HPC and AI/ML applications.
Rambus CryptoManager for enhanced security
Rambus has announced the CryptoManager Root of Trust RT-640 and RT-645 cores have been certified ASIL-B and ASIL-D ready, respectively. These automotive-grade secure co-processor IP safeguards SoCs in V2X communications, ADAS, ECU platform management, infotainment and other critical vehicle systems.
Pushing the envelope for ADAS with advanced memory technologies
Driver assistance systems such as cruise control are now part of the standard specification in a modern vehicle. ADAS Level-2 (L2), partial automation, and the first Level-3 (L3) conditional automation systems are in the market, but the journey to full automation still has some years to go. Here, Frank Ferro, Senior Director of Product Marketing for IP cores at Rambus explains.
800G MACsec solution for 5G infrastructure security
Rambus has announced its 800G MACsec (Media Access Control security) solution for next-generation networking infrastructure. The 800G MACsec solution delivers hardware-based, point-to-point security for 800 Gigabit Ethernet links and is a critical element of end-to-end network security.
Complete interface solution for HBM2E memory launched
Rambus has announced a comprehensive interface solution for HBM2E memory consisting of co-verified PHY and memory controller. Operating at a top speed of 3.2 Gbps over a 1024-bit wide interface, the interface can deliver 410 GB/s of bandwidth with a single HBM2E DRAM stack.
Memory subsystem solution for next-generation AI training chip
Rambus has announced that Enflame (Suiyuan) Technology has selected Rambus HBM2 PHY and Memory Controller IP for its next-generation AI training chip. Rambus memory interface IP enables the development of high-performance, next-generation hardware for leading-edge AI applications.
Portfolio of advanced memory and SerDes PHYs on TSMC N7 process
Rambus has announced a broad portfolio of high-speed memory and SerDes PHYs for next-generation applications on TSMC’s industry-leading N7 process technology. Rambus offers GDDR6, HBM2 and 112G LR PHY IP available for licensing, these solutions enable demanding applications for data centre, networking, wireless 5G, HPC, ADAS, AI and ML.
Advancing AI with faster memory systems
Steven Woo of Rambus explains some of the challenges to closing the AI memory gap. Over the last 15 years the use of artificial intelligence (AI) techniques has boomed. We now carry AI assistants in our pockets, trust algorithms to provide image recognition in autonomous vehicles and use machine learning to predict the spread of disease. The development of these modern AI applications has only come about because of advances in AI algorithms,...
Leading-edge 7nm process node for PPA
Rambus has announced the tapeout of its 112G XSR SerDes PHY on a 7nm process node optimised for PPA. As the industry continues to adopt chiplet architectures for networking and compute applications, the Rambus 112G XSR SerDes PHY represents the latest advancement in high-speed signalling technology for die-to-die (D2D) and die-to-optical engine (D2OE) connections.
Securing systems: Four top tips for design engineers
Scott Best, Technical Director of Anti-Counterfeiting Products, Rambus, explains the role of cryptographic ICs. As system counterfeiting attacks continue to send shockwaves across industries, design engineers are evaluating how best to deploy cryptographic authentication integrated circuits (ICs) to secure systems. While there is no shortage of options available, in reality many of these solutions provide very poor levels of additional secur...
Power efficiency for SoCs in data-intensive applications
The newest portfolio solution of 112G Long Reach (LR) SerDes PHY on a leading-edge 7nm process node for next-generation terabit switches, routers, optical transport networks (OTNs), and high-performance networking equipment, has been announced by Rambus.
GDDR6 PHY IP on seven nanometre process technology
The tapeout of its GDDR6 PHY on TSMCseven nanometre FinFET process technology has been announced by Rambus, and is available from Rambus for licensing today. Leveraging almost 30 years of high-speed interface design expertise and using advanced process technology, Rambus has successfully taped out a GDDR6 PHY IP on TSMC seven nanometre process technology.
Innovative technology acquisition to expand Flash memory offerings
The company dedicated to making data faster and safer, Rambus, has announced that it has acquired the assets of Diablo Technologies to broaden its portfolio in the hybrid DRAM and Flash memory markets. These patented innovations augment the existing Rambus NVDIMM portfolio and complement its high-bandwidth, low-power memory technologies.
CryptoManager platform selected for Authenta technology
Rambus has announced that Micron Technology has selected the Rambus CryptoManager Platform for Micron’s Authenta secure memory product line to enable a new level of protection for the Internet of Things (IoT) devices.
Mitigating security vulnerabilities like Meltdown and Spectre
Rambus has announced the availability of the CryptoManager Root of Trust, a fully programmable hardware security core built with a custom RISC-V CPU. The secure processing core creates a siloed architecture that isolates and secures the execution of sensitive code, processes and algorithms from the primary processor.
Rambus develops hybrid memory system for future data centers
Rambus has announced a collaboration with IBM to research hybrid memory systems. Targeting one of the industry’s key performance challenges, Rambus Labs and IBM aim to optimise the use of DRAM and emerging memories to create a high-capacity memory subsystem that delivers comparable performance to DRAM alone.
Memory solution supports AI automotive and networking applications
The new GDDR6 (Graphics Double Data Rate) Memory PHY IP Core has been announced by Rambus, which is targeted for high-performance applications including cryptocurrency mining, artificial intelligence (AI), ADAS (advanced driver assistance systems) and networking.
Rambus partners with Samsung to develop 56G SerDes PHY
Rambus has announced that it is partnering with Samsung Electronics for its recently launched 56G SerDes PHY to be developed on Samsung’s 10nm LPP (Low-Power Plus) process technology. The industry-leading 56G SerDes PHY delivers enterprise-class performance across the challenging signaling environments typical of high-speed communication systems and provides PAM-4 and NRZ signaling with a scalable ADC-based (analog-to-digital converter...
Rambus expands cryogenic memory collaboration with Microsoft
Rambus has announced an expanded collaboration with Microsoft researchers to develop prototype systems that optimise memory performance in cryogenic temperatures. Following the initial collaboration announced in December 2015, this new agreement extends joint efforts to enhance memory capabilities, reduce energy consumption and improve overall system performance.
Unified Payment Platform allows users to digitise credit cards into secure retail wallet
A comprehensive mobile payments platform has been announced by Rambus. It will enhance payment security, reduce operational costs and increase revenue for retailers. The Rambus Unified Payment Platform securely converts and manages digital value to enable consumers to pay with credit, points and coupons in a single transaction and transform how they shop and pay.