Leading-edge 7nm process node for PPA

30th September 2019

Rambus

Alex Lynn

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Rambus has announced the tapeout of its 112G XSR SerDes PHY on a 7nm process node optimised for PPA. As the industry continues to adopt chiplet architectures for networking and compute applications, the Rambus 112G XSR SerDes PHY represents the latest advancement in high-speed signalling technology for die-to-die (D2D) and die-to-optical engine (D2OE) connections.

Rambus continues at the forefront of implementing 112G designs to address the needs for next-generation data-intensive applications.

In today’s increasingly connected world, zettabytes of data are generated constantly by a wide range of devices including IoT endpoints such as vehicles, wearables, smartphones and appliances. AI and ML add new workloads and new data streams from the data centre to the edge, driving new architectures to move data. These new architectures, combined with the trend toward chip disaggregation and the industry’s transition to 400Gb and 800Gb Ethernet, will require new, faster interconnect solutions.

"As semiconductor markets turn towards chiplets to enable their high-performance products, chip-to-chip interconnects will be critical for maintaining high speed and signal integrity across variable physical distances," said Shane Rau, Research Vice President, Computing Semiconductors at IDC. "SerDes PHYs at advanced process nodes, like the 7nm 112G XSR, enable that speed and signal integrity."

“Our 112G XSR SerDes PHY is implemented in the leading-edge 7nm process technology, providing chip and system architects the most advanced platform for their designs,” added Hemant Dhulla, Vice President and General Manager of IP cores at Rambus. “We are excited to continue our tradition of delivering leading-edge IP solutions that address the systems design challenges of the most demanding applications in networking, HPC and AI.”

The Rambus 112G XSR SerDes PHY will deliver enterprise-class performance within D2D and D2OE interconnects for 400Gb and 800Gb Ethernet environments. To achieve the demanding data rates of these high-speed applications requires an innovative SerDes architectural approach.

The Rambus 112G XSR SerDes PHY includes:

High-bandwidth connectivity greater than 800 Gbps per millimetre of beachfront making it well suited for D2D and D2OE interconnects in networking and HPC applications.
Designed to provide a low-power, high-speed interface that supports chip disaggregation.
Good architecture for power, performance, area (PPA) with approximately 1 pJ/bit or 1mW/Gbps power.
Compliance with Open Interface Forum Common Electrical I/O Consortium (OIF-CEI) standard.