The data centre industry is approaching a hard limit: the mechanisms that historically delivered exponential gains in compute performance are no longer working.
For decades, semiconductor progress was underpinned by Dennard scaling, the principle that shrinking transistors would simultaneously increase performance and maintain power density. This enabled a simple and powerful assumption: each successive generation of silicon would deliver more compute at roughly the same energy cost.
That assumption no longer holds. Since the mid 2000s, power density constraints have broken this relationship, forcing a shift from frequency scaling to multicore designs, and, ultimately, to leaving increasing portions of silicon idle. What began as a device-level constraint has become a system-level limitation: additional silicon no longer translates into usable performance.
The consequence of the breakdown in Dennard scaling is the emergence of ‘dark silicon’: the reality that only a fraction of transistors on a chip can be active simultaneously without exceeding thermal limits. Increasing transistor count no longer translates linearly into usable performance, because power, not area, has become the primary constraint.
Attempts to recover performance through multicore scaling have only partially mitigated this effect. While adding cores increases theoretical throughput, it also increases total power consumption, increasing total power draw until thermal limits are hit. The result is a system in which a significant fraction of available compute cannot be used simultaneously.
These constraints propagate directly to the data centre. If additional silicon cannot be fully powered or efficiently utilised, then simply deploying more advanced chips does not produce proportional gains in capacity. At the same time, scaling out infrastructure, building larger data centres, runs into a separate but related limit: the availability and cost of energy. What was once a device-level optimisation problem now defines the economic limits of compute at the system level.
The data centre impact
If organisations can no longer rely on chips getting naturally faster and more powerful every year, data centres are the first to be affected.
They are constrained first by the failure in performance scaling: as it becomes increasingly difficult to extract more usable performance from the same silicon area while staying within power limits, deploying newer generations of chips no longer delivers proportional gains.
They are then constrained by the limitations of multicore scaling: building larger or denser chips increases theoretical throughput but does not guarantee usable performance at system level due to power and utilisation limits.
Finally, scaling out to larger facilities encounters a separate constraint: energy availability. The industry has attempted to compensate for reduced efficiency at the chip level by increasing scale at the system level, but this approach runs into fundamental limits in power supply and cost.
These pressures are compounded by accelerating demand for AI workloads, which continue to push infrastructure requirements upward even as the efficiency of scaling declines. Taken together, this creates a structural problem: it is no longer economically viable to scale compute in the way the industry has historically done.
And compounding each of these issues is the insatiable demand for AI. Gartner projects revenues from semiconductors used in AI will reach $120 billion by 2027, up from $44 billion in 2022.
The shift exposed by AI
These constraints are now being exposed most clearly by AI workloads, which demand both scale and efficiency. Recent thinking in the field assumed that increasing model size, more parameters, more compute, would continue to yield proportional gains in capability. However, evidence is emerging that these returns are diminishing, and that simply scaling model size is no longer sufficient to drive meaningful improvements.
This changes the optimisation problem: rather than increasing total compute, the focus shifts to extracting more capability from a fixed compute budget.
In response, a class of efficiency-driven techniques has begun to emerge. Model distillation, for example, allows smaller models to inherit the behaviour of larger ‘teacher’ systems, approaching their accuracy while significantly reducing the computational cost of deployment. Similarly, work on memory efficiency, such as optimising the handling of key-value caches, demonstrates that substantial reductions in resource requirements can be achieved without degrading output quality.
MIT’s Frankle & Carbin’s ‘The Lottery Ticket Hypothesis’ suggests that large language models contain smaller, highly efficient representations within them. Work on model compression and pruning has shown that smaller subnetworks can retain much of the original model’s capability while requiring a fraction of the resources. This phenomenon reinforces the broader point: the limiting factor is no longer access to more parameters, but the ability to identify and exploit efficient structure within existing ones.
In response, a class of efficiency-driven techniques has begun to emerge. It argues that within the embodiment of a large LLM, there exists a perfect subnet form, that is a fraction of the size.
Model distillation, is another example, allowing smaller models to inherit the behaviour of larger ‘teacher’ systems, approaching their accuracy while significantly reducing the computational cost of deployment. Similarly, work on memory efficiency, such as optimising the handling of key-value caches, demonstrates that substantial reductions in resource requirements can be achieved without degrading output quality.
More recently Google’s TurboQuant paper demonstrates very efficient compression of Key, Value pair (KV) caches. On release, the paper was cited by the press as explaining a sharp drop in the share prices of key memory suppliers. The paper explored tuning for KV caches, used to retain the context of current task an LLM model is being applied to. The problem is decent sized context takes up a lot of RAM. By tuning the way LLMs encode the KV cache information, it was possible to achieve identical results with a fraction of the RAM.
Taken together, these developments indicate a shift away from brute-force scaling towards algorithmic and architectural efficiency. Capability is no longer tied linearly to model size or raw compute, but increasingly to how effectively that compute is used.
Efficiency as evidence, not aspiration
Recent models such as DeepSeek V3 provide a clear illustration of this shift. Despite achieving performance comparable to leading closed models in several benchmarks, DeepSeek V3 was trained at a reported cost of approximately $5-6 million, an order of magnitude lower than the estimated cost of GPT 4 class systems. This efficiency is enabled by a combination of architectural choices, including sparse mixture of experts designs in which only a subset of parameters are active for each token, and training techniques that improve utilisation of available hardware.
The implication is not simply that one model is more efficient than another, but that the underlying economic model of AI is changing. It is increasingly possible to achieve high levels of capability without scaling compute in proportion, undermining the assumption that progress depends on ever-larger deployments of hardware. It demonstrates that improvements in capability are increasingly being decoupled from proportional increases in compute.
Architectural consequences
These shifts have architectural consequences. As models become more efficient, inference is no longer constrained to large-scale, centralised data centres. Instead, computation can increasingly move closer to the point of use, toward edge environments where latency, power efficiency, and data privacy are critical constraints.
This does not eliminate the role of the data centre, but it changes its function: from the primary locus of inference to a hub for training, coordination, and high-end workloads that cannot yet be efficiently distributed.
Conclusion
The cumulative effect of these trends is clear: the ‘bigger hammer’ model of compute scaling is reaching its limits. Simply adding more transistors, more cores, or more servers no longer deliver proportional gains in capability, because the underlying constraints, power, efficiency, and utilisation, now dominate system behaviour.
The alternative is not incremental improvement, but a shift in emphasis. Future systems will need to prioritise efficient data movement, selective activation of compute resources, and architectures that are explicitly designed around power and memory constraints rather than peak throughput. This requires a rethinking of both hardware and algorithms, not as independent layers, but as a co-designed system.
The industry has spent two decades optimising for scale. The next phase will be defined not by how much compute can be deployed, but by how efficiently it can be used.
