Software encryption feature protects FPGA IP

24th June 2015
Posted By : Mick Elliott
Software encryption feature protects FPGA IP

Support for the Advanced Encryption Standard (AES) for the 7 Series FPGAs has been announced by Goepel Electronics. The AES feature is designed for better protection against potential attackers and theft of intellectual property from within the FPGA. The Xilinx AES programmer by GOEPEL electronics is integrated into the standard JTAG/Boundary Scan software platform SYSTEM CASCON.

It allows programming of the so-called eFUSE register, including a 256bit AES key, via secure JTAG access.

The On-Time Programmable eFUSE register is uniquely configured, after arming the FPGA can only accept the encoded bit streams, as the arming of the AES mechanism is an irreversible process. This results in maximum security during the authentication and encryption of your FPGA programming data, as well as once it is safely locked within the device.

Since the Xilinx AES Programmer is native part of the SYSTEM CASCON ISP tool suite the downloading of the encrypted programming data can then be executed on the same platform after the unique AES configuration has been completed.

High speed hardware with essential production line reliability and stability is provided through the use of the JTAG/Boundary Scan platform SCANFLEX. The system offers many possibilities to cover different applications, such as true parallel programming of multiple devices, 16+, and operation of the JTAG interfaces over long distances and through pin bed fixtures, with no loss of signal integrity, using differential pairs to connect to the target system(s).

Both the hardware and software fully support the all the other advanced technologies from the GOEPEL Embedded System Access platform, so that the combination of other test procedures such as Boundary Scan, Processor Emulation Test and even Bit Error Rate testing of high speed busses on the board are also possible using the same system.


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