New Mux & Demux for Broadband Test, ATE, FPGA & DAC Interfacing

The HMC954LC4B is a 32 Gbps 2:1 Multiplexer which time interleaves two differential input data lanes up to 16 Gbps, into a single output data lane up to 32 Gbps. The mux latches the two differential inputs on a rising edge of the input clock and the device uses both rising and falling edges of the half-rate clock to serialize the data. The HMC955LC4B is a 1:2 Demultiplexer which is designed to deserialize a single input data lane up to 32 Gbps into two separate output data lanes up to 16 Gbps each. The device uses both the rising and falling edges of the half-rate input clock, typically 16 GHz, to sample the input data in sequence, and latches the data onto the differential outputs. The HMC955LC4B also features a high speed clock synchronous invert input that allows for data scrambling.

Both the HMC954LC4B and the HMC955LC4B are capable of operating from either a negative or positive 3.3V supply while exhibiting only 0.2 ps RMS jitter and 3 ps p-p of deterministic jitter. These specifications, combined with low typical power dissipation of 500 mW and low skew between outputs, make them ideal for data aggregation and data source selection in military and communications systems. Fast rise and fall times of 19 ps, programmable output voltage swing capability and DC coupling enables simple interfacing with FPGA devices in ATE applications.

The HMC954LC4B and the HMC955LC4B complement many of Hittite's previously released Fiber Optic and High Speed Logic products, are housed in ceramic 4 x 4 mm SMT packages (RoHS compliant), and are fully specified for operation from -40 °C to +85 °C. Samples and evaluation PC boards for all SMT packaged products are available from stock and can be ordered via the company's e-commerce site or via direct purchase order.