AES programming tool guards against IP theft
The Spartan-6 FPGAs by Xilinx are protected against potential attackers and theft of IP (Intellectual Property) through the so called AES Programmer (Advanced Encryption Standard) from Goepel electronic. The Xilinx Spartan-6 AES Programmer by GOEPEL electronic is a tool integrated into the JTAG/Boundary Scan software platform SYSTEM CASCON. It allows programming of the so-called eFUSE register, including a 256bit AES key, via secure JTAG access.
The One-Time Programmable eFUSE register is uniquely configured. After arming, the FPGA can only accept the encoded bit streams, as the arming of the AES mechanism is an irreversible process.
This results in maximum security during the authentication and encryption of the FPGA programming data, as well as once it is safely locked within the device. The One-Time Programmable (OTP) eFUSE register can be precisely configured.
This is essential because the arming of an AES mechanism is an irreversible process. After arming only properly encoded bitstreams are accepted by the FPGA.
High speed hardware with essential production line reliability and stability is provided through the use of the JTAG/Boundary Scan platform SCANFLEX.
The system offers many possibilities to cover different applications, such as true parallel programming of multiple devices and operation of the JTAG interfaces over long distances and through bed-of-nails fixtures, with no loss of signal integrity, using differential pairs to connect to the target system(s).
AES is an official standard, supported by the National Institute of Standards and Technology and the U.S. Department of Commerce.
By using the Xilinx AES feature the FPGA design of the Spartan-6 is protected against potential attackers. Without corresponding AES keys, bit streams cannot be analysed, whereby the encrypted designs are hedged against re-engineering, cloning and copying.
Both the hardware and software fully support all other advanced technologies from the GOEPEL Embedded System Access platform, so that the combination of other test procedures such as Boundary Scan, Processor Emulation Test and even Bit Error Rate testing of high speed busses on the board are also possible using the same system.