Quantum Tech

Main challenges facing large-scale Si quantum computing

16th December 2021
Beatrice O'Flaherty

CEA, in collaboration with CNRS Néel, a team in SI-based quantum computing, presented two papers on that topic at IEDM 2021, including an invited paper that identifies the material and integration challenges facing large-scale Si quantum computing.

The second paper presents a novel Si quantum device integration that reduces by half the effective gate pitch and provides full controllability in 1D FD-SOI quantum dot (QD) arrays.

The invited paper, 'Material and integration challenges for large scale Si quantum computing', was featured in a special Focus Session, 'Device Technology for Quantum Computing', at the Dec. 11-15 meeting.

Presented by Maud Vinet, director of CEA-Leti’s quantum computing program, the paper notes that Si spin qubits are “very promising” for enabling large scale quantum computing because they are fast and small and of high quality.

“They also derive directly from advanced CMOS technologies, which is good news for scalability,” said Vinet, the lead author of the paper. “So, tomorrow’s universal quantum computing could very well be silicon. However, while other approaches that rely on superconductors, cold atoms and trapped ion-based qubits have shown noteworthy results, silicon spin qubits are still lagging behind with only three-qubit gates demonstrated so far,” she said. “There are still material and integration challenges to be tackled before fully expressing their potential.”

Material challenges include development for the channel. For example, isotopically purified Si and Si/SiGe stacks will provide nuclear spin-free active substrates and significantly increase coherence times. The supply chain remains a challenge for acquiring these materials, which could limit their use on a large scale. Vinet said specifications for the isotopic purity of the materials have yet to be confirmed, and the best integration scheme to ensure immunity to 29Si diffusion is still an open question.

“The requirements for the gate stack are also unforgiving: namely, low or even very low charge defects at the channel interface, compatibility of the thermal expansion coefficients across the whole gate stack to avoid local potential peculiarities due to strain, and low metal gate granularity to achieve record variability,” she explained.

Integration challenges are new layouts, new process-flow integration and the need for 3D integration, and they will require a statistical characterization platform all the way to low temperature. In the past few years, CEA-Leti has made progress in all these directions: setting up a 28Si supply chain and proposing integration flows in SOI wafers. A simulation framework has been set up to help provide specifications on the gate stack, and a 300mm flow featuring 40nm effective pitch has been developed to provide up to 16 qubits.

Vinet explained that silicon spin qubits have demonstrated “some promising properties” at the individual level, including small footprint, fidelity, speed of all operations and temperature of operation. “We have now identified the key material and integration challenges to overcome in order to increase the qubits number and quality, although the technology is beleaguered by a late start and high barriers to entry,” she said.

CEA-Leti’s quantum computing R&D is supported by the institute’s extensive experience in materials, e.g. epitaxy and gate stack and integration expertise in SOI, cryo-CMOS, 3D integration and advanced packaging.

A related paper by Vinet, “The path to scalable quantum computing with silicon spin-qubits”, was published earlier this month in Nature.

A second paper presented at the conference, “A new FD-SOI spin qubit platform with 40nm effective control pitch, notes that operating Si quantum dot (QD) arrays requires homogeneous and ultra-dense structures with aggressive gate pitch. Such a density is necessary to separately control the quantum dots’ chemical potential, i.e. the charge occupation of each dot, from the exchange interaction, or the tunnel barriers between each one.

The research team developed the novel Si quantum-device integration that halves the effective gate pitch and provides full controllability in 1D FD-SOI QD arrays. The design targets were established thanks to numerical simulations, then the fabricated structure’s functionality was validated via 300K statistical electrical characterisation, while tunnel-coupling control was demonstrated at cryogenic temperatures.

“This is the first demonstration of electrostatic coupling control over QD systems implemented in CMOS SOI devices by means of back biasing and the use of exchange gates,” said Thomas Bédécarrats, a CEA-Leti scientist and lead author of the paper.

“It is a first step towards a successful control of spins for qubit applications. We drew on CEA-Leti’s new immersion DUV lithography capability to achieve small features with low variability at throughputs compatible with volume production,” Bédécarrats added. “In terms of potential scalability, the process flow used in this research is very similar to standard CMOS technologies. We also added exchange gates that intertwine with the front gates to enable separate control of the tunnel barriers’ and quantum dots’ chemical potentials.”

The resulting CEA-Leti 300 mm FD-SOI spin-qubit platform, which includes two gate layers, is fully compatible with industry processes.

The paper notes that “one of the major advantages Si offers in comparison to other platforms is its scalability.” Indeed, error-free quantum computing relies on the use of quantum error correction algorithms, which requires the control of millions of qubits. On silicon spin-qubits platforms, making millions of qubits is similar to making millions of transistors, the paper says. Such a platform will benefit from the semiconductor industry’s decades of experience making large volumes of small, dense devices reproducibly.

“The results we present at IEDM 2021 are on par with other research groups’ spin qubit demonstrations, and they confirm the advantage of using CMOS-like platforms,” Bédécarrats said. “However, a high density of qubit devices infers that at least as many ways of control over those qubits are required, which is challenging from an integration perspective.”

CEA-Leti’s partners in the two projects were Université Grenoble Alpes, CNRS Institut Néel and CEA-Irig. The research was partially supported by the EU through the H2020 QLSI project and the European Research Council (ERC) Synergy QuCube project.

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