Design

Optimised architecture targets high performance applications

23rd June 2016
Joe Bush
0

An optimised version of the DesignWare PHY and Controller IP Solution for PCI Express (PCIe) 4.0 architecture has been released by Synopses, which reduces latency by up to 20% and area by 15% compared to the previous implementation.

The PCI Express PHY and Controller IP supports lane margining, allowing system designers to assess performance variation tolerance for design robustness. By supporting the latest PCI Express 4.0 specification, the DesignWare IP solution provides proven interoperability and addresses the stringent performance requirements of cloud computing and automotive applications.

“Synopsys’ DesignWare PHY and Controller IP for PCI Express 4.0 technology has been tested for interoperability using the Teledyne LeCroy Summit Z416 Protocol Analyzer/Exerciser, which is targeted to test for PCIe 4.0 compliance in the near future,” said John Wiedemeier, Product Marketing Manager at Teledyne LeCroy. “This is an important indicator to all designers and the ecosystem that the DesignWare IP works as expected and meets the latest PCI Express specification requirements, mitigating risk and accelerating time to market.”

In the transition from the PCI Express 2.0 to PCI Express 3.0 specification, increases in speed, protocol changes and new equalisation schemes led to design complexities and silicon issues. To ease the transition to the PCI Express 4.0 architecture, to provide more visibility into the performance of the interface, and to help designers to quickly diagnose issues and validate silicon, Synopsys offers extensive error injection and debug capabilities for silicon analysis along with built-in self-test (BIST) and automatic test equipment (ATE) test vectors for a complete at-speed production testing. In addition, designers can utilise Synopsys’ IP Prototyping Kits and IP Virtualizer Development Kits for PCI Express 4.0 technology to accelerate their SoC and software development.

“Our customers are consistently challenged with meeting their design performance and area requirements for advanced data intensive cloud computing applications,” said John Koeter, Vice President of Marketing for IP and Prototyping at Synopsys. “By providing an optimised PCI Express IP solution that significantly reduces latency and area, Synopsys is enabling designers to meet their key design requirements and deliver differentiated products.”

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