Design

Everything is a network

5th August 2014
Nat Bowers
0

We are entering a new era in networking, where processing is being pushed to the edge and nodes are starting to look more like networks in their own right. Philip Ling, Editor, ES Design magazine, reports.

When homogeneous multicore technology really took hold, around a decade ago, it targeted packet processing. Today, multicore processors are more commonplace outside this space, but they remain strong in communications purely because they offer the performance needed to meet today’s networking requirements. The pressure placed on processor vendors is only going to increase as demand for more bandwidth builds, but it is widely believed that multicore doesn’t scale in the same way as demand; devices with eight cores are essentially where the productivity benefits end. So what are manufacturers doing to overcome the roadblock?

Some, like Freescale, have already started. It announced its core-agnostic Layerscape architecture around two years ago and stated then that it would allow both ARM and Power cores to be used. To date, the company hasn’t developed a Layerscape-based QorIQ device that isn’t ARM-enabled, but Tom Deitrich, Senior Vice President & General Manager, Digital Networking Group, stated that the Power architecture remains ‘the standard’ in networking and developers are going to take time to migrate over to ARM, adding that ARM isn’t as mature in this space yet.

During FTF 2014, Freescale announced the second generation of QorIQ devices built on Layerscape, the LS2, which employs up to eight 64-bit Cortex-A57 cores (Figure 1). This is coupled to a set of debug and acceleration technologies, which includes a packet processing engine that is C-programmable and supported by a toolkit of turnkey C-based libraries featuring common networking protocols and functions. An L2 switch is also integrated alongside the datapath engine, which results in a System-on-Chip.

Figure 1 - Freescale's second generation Layerscape technology

Figure 1 - Freescale's second generation Layerscape technology

Also announced during FTF 2014 was Freescale’s acquisition of the Comcerto CPE communications processor business of Mindspeed Technologies, which comprises the company’s multicore ARM processors and associated software. Gregg Lowe, President & CEO of Freescale, described the devices as filling gaps in the LS1 portfolio at the low-end. Based in India, the business is located physically close to an existing Freescale office, making integration simpler, explained Lowe.

Multicore max

While the LS2 devices integrate up to eight ARM cores, Freescale’s Senior Marketing Manager, Matt Short, explained that multicore technology has effectively reached its limits in both hardware and software; a ‘many-core’ approach is unsustainable due to power, software complexity and integration costs. The answer, Freescale believes, is providing the right mix of high performance and programmability. This is basically the philosophy than underpins Layerscape, and the latest incarnation relies as much on an advanced packet processing architecture as it does on the 64-bit multicore processing sub-system.

As Figure 2 shows, Layerscape’s architecture relies on optimised packet processing engines but also highlights the need to stay on-chip; the performance penalty related to DDR memory is clear to see and Short stated that as soon as you go off-chip, you’ve ‘lost the battle’. However, attempts to make multicore devices in the past have invariably incurred increased software complexity, so Freescale is keen to stress how ‘C-friendly’ the LS2 is.

Figure 2 - Going off-chip now represents the most significant bottleneck to performance

Figure 2 - Going off-chip now represents the most significant bottleneck to performance

To achieve this, it has implemented what Short refers to as a Management Complex; a hardware-based kernel/API that runs software and is accessible, but effectively raises the level of abstraction for programmers, allowing the device to be targeted with standard C code. The result is a platform with a datapath that has been ‘designed with software developers in mind’. The data path hardware is abstracted, called using standard Linux objects. The acceleration delivers 40Gbps packet processing performance with 20Gbps acceleration of tasks such as pattern matching and data compression.

The QorIQ LS2 family has been designed specifically for Software Defined Networking (SDN) and open-standard protocols such as OpenFlow switching, as well Network Function Virtualisation (NFV) solutions, wireless access, enterprise routing and data centre processing applications. Further Cortex-A based multicore processors are to be disclosed later in 2014, according to Freescale, while the company continues to expand the Power Architecture-based QorIQ portfolio with three new T Series processors, targeting smart edge WLAN access points and branch routers, as well as providing an upgrade path for P1 and PowerQUICC users.

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