Design
100 Tapeouts Underscore Rapid and Broad Acceptance of Synopsys' In-Design Physical Verification
Synopsys today announced that its award-winning Galaxy Implementation Platform product, IC Validator, for In-Design physical verification within IC Compiler, has been successfully used for more than 100 tapeouts at advanced process nodes. Coming so soon after IC Validator's 2009 launch, this milestone is a strong indicator of the requirement for a different physical verification use model. In contrast to the traditional stand-alone physical verif...
Learn how to quickly and easily parallelize your embedded multicore programs at Embedded Live
Vector Fabrics will be hosting a conference session titled Simplifying the Hard Part of Multicore: Partitioning Code at the forthcoming Embedded Live conference. Recognizing that one of the barriers slowing the transition to embedded multicore is the difficulty of parallelizing your functionality, the session will highlight why manual partitioning is so hard, and will introduce a new methodology and tool that directly addresses the challenge of p...
Xilinx ISE Design Suite 12.3 Introduces AMBA 4 AXI4 IP Cores, Enhances PlanAhead Design and Analysis Cockpit, Extends Power Optimization
Xilinx announced the release of ISE Design Suite 12.3, kicking-off the FPGA leader's roll-out of Intellectual Property (IP) cores that meet the AMBA(R) 4 AXI4(TM) specification for interconnecting functional blocks in System-on-Chip (SoC) design, as well as introducing productivity enhancements to the PlanAhead(TM) Design and Analysis cockpit, and Intelligent Clock Gating support for reducing dynamic power consumption in Spartan(R)-6 FPGA designs...
Altera Launches Embedded Initiative with New System Level Integration Tool for Embedded Systems Configurability
To accelerate the integration of programmable logic and processors in embedded systems, Altera Corporation today announced its Embedded Initiative. With this initiative, Altera is providing designers a single FPGA design flow based on its Quartus® II development software—including the new Qsys system-level integration tool, a common FPGA intellectual property (IP) library, and new ARM® Cortex™-A9 MPCore™ and MIPS® Te...
3D drawings online
LEMO S.A has added an entire range of 3D drawings on tracepartsonline.net. Traceparts is one of the biggest parts libraries in the world, offering 100 million free 2D drawings & 3D CAD models
Lauterbach Announces Support for the New Intel Atom Processor E6xx Series
Lauterbach, the leading manufacturer of hardware assisted microprocessor development tools, has announced today support for the new Intel® Atom™ processor E6xx series formerly known as Tunnel Creek.
Cadence Offers Optimized Implementation Methodology for Silicon Realization of New ARM Cortex-A15 MPCore Processor
Cadence Design Systems today announced it is providing its customers an optimized implementation methodology for the new ARM® Cortex™-A15 MPCore™ processor that enables them to start designing Cortex-A15 processor-based SoCs immediately. As ARM developed the Cortex-A15 MPCore processor - its most advanced processor for mobile, consumer and infrastructure applications - Cadence® worked alongside the microprocessor IP leader to develop the me...
SMIC Adopts Cadence Silicon Realization End-to-End Product Line for 65-40nm Design
Cadence Design Systems today announced that the most advanced foundry in Mainland China, Semiconductor Manufacturing International Corporation (“SMIC”, NYSE: SMI and SEHK: 0981.HK), has adopted the Cadence Silicon Realization product line for advanced node, low-power designs. The Cadence Silicon Realization product line is composed of tools essential to turning designs into silicon. It is a key element of its EDA360 (the new Electronic Design...
Global Unichip Expands Portfolio of Cadence Technology to Speed IP Development
Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced that Global Unichip Corporation (GUC) has adopted Cadence® Virtuoso® custom design technologies to speed development of its high-speed interface IP. GUC also has adopted Cadence design for manufacturing (DFM) technologies for its advanced process node system-on-chip (SoC) designs.
UL releases white paper for safer household electronic appliance design
Today, Underwriters Laboratories (UL), a world leader in safety testing and certification, released The Increasing Complexity of Appliance Motors: The Need for New Standards to Address New Technologies, a white paper that reviews the evolution of small motor design, emerging motor protection schemes and the applicable standards for safer design and operation.