Global Unichip Expands Portfolio of Cadence Technology to Speed IP Development

Cadence has long been GUC’s primary EDA vendor, assisting with design implementation for successful GUC tapeouts at various process nodes. With the adoption of Cadence custom design and DFM technology, GUC has developed a variety of high-speed interface IP to help its customers achieve Silicon Realization, a key element of the EDA360 vision.

“GUC is committed to providing the most advanced and cost-effective silicon solutions. After collaborating with Cadence, we can further strengthen our IP development capabilities,” said Jim Lai, president of Global Unichip Corporation. “Our high-speed interface IP development continuously helps our customers achieve Silicon Realization in high-speed networking, video processing, and mobile handset products. Moreover, Cadence’s leading custom design and DFM technologies, and strong support help ensure tough design challenges are resolved at early stages in the SoC design cycle, and facilitate the IP qualification process.”

GUC has adopted Cadence Virtuoso Multi-Mode Simulation (MMSIM) for top-level co-simulation between logic and analog circuits to help guarantee their functions before tape-out, and the Virtuoso Layout Suite for streaming the layout for viewing. MMSIM enables GUC to construct the architecture that can meet their specifications before designing sub-blocks. MMSIM also provides a unique environment that interfaces with a common usage model, cross-probing, and back-annotation capabilities which allow fast customer adoption. This solid top-down design approach can shorten the design cycle and the time to market.

In addition to the top-down design approach, GUC also has adopted CMP Predictor as its standard sign-off tool at the 65-nanometer process node to avoid hotspots, and Litho Physical Analyzer (LPA) as its signoff tool at 40 nanometers to achieve litho-hotspot-free design. GUC achieved greater results by using Cadence DFM-aware solutions such as CMP Predictor and LPA to turn the uncertainty of manufacturing process variations into predictable impacts, and to minimize the impacts during the design stage.

CMP-related hotspots, such as copper pooling, can have detrimental effects on chip yield. In addition, LPA—which helps to quickly and accurately account for systematic manufacturing variations—enables GUC designers to analyze the litho impact on transistor performance and make necessary design tradeoffs to meet their design criteria and improve yield during physical implementation.

“We are pleased that GUC has verified the value of our MMSIM and DFM technology and expanded our collaboration,” said Willis Chang, country manager of Cadence Taiwan. “As GUC’s primary EDA vendor, Cadence provides a new user interface which greatly simplifies the complex tasks analog designers must perform. The integrated DFM features further enhance the Virtuoso platform in aiding the development of high-speed interface application IP.”