MiP is unique in the way it performs user authentication. During an authentication process, the direct bit-to-bit comparison of the stored reference pattern to be authenticated occurs within the memory array. This is unlike traditional methods. In traditional read functions, the secret keys stored in other memory types need to be downloaded from the memory and cached in a register where switching operations could be analyzed. Whereas in the new MiP approach, the sensitive data stored in a Magnetic Logic Unit array is never revealed to an external bus or register. This makes the security more robust.
In addition, it takes MiP less than 70 ns to perform a user authentication match. Therefore, the window of opportunity to carry out a security attack is significantly reduced or virtually non-existent.
The MiP prototype has a maximum of 32-bits of MiP to demonstrate a 4 – 10 digit PIN code match. Crocus will make MiP available as a FPGA demonstrator in Q3 2013.
“We believe strong authentication, beyond existing solutions, is essential for better security, enhanced privacy and more secure transactions,” said Alain Faburel, vice president security business unit at Crocus. “With Match in Place, Crocus continues to build upon its innovations for mobile applications. We are pleased to provide the digital security market with an efficient technique that makes user authentication faster and safer.”
The unique security function and speed of MiP make it ideal for protecting PIN codes and access ID from theft or unauthorized use when connecting to an external device, such as a smart card reader. It is suitable for biometrics, where MiP will perform the biometric pattern recognition within the smart card in an extremely fast time of less than 70 ns.
MiP is based on Crocus’ breakthrough Magnetic Logic Unit, a CMOS based rugged magnetic technology. As a result, MiP draws benefit from many of MLU’s advantages. These include reading and writing faster than flash memory as well as its small footprint.
Each cell of the MiP technology is a non-volatile memory cell combined with the virtual XOR gate (digital logic gate) of the MLU. Multiple cells are connected in series to a NAND chain acting as a linear MiP engine. In digital electronics, a NAND gate is used to accomplish bit-to-bit comparisons. If multiple MiP NAND chains are placed in parallel, they can act simultaneously to compare one pattern against many.