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Arithmetic processing IP core for MP3 decoders features smallest circuit size and lowest power consumption

12th July 2010

Murata Electronics (UK) Ltd.

ES Admin

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Murata, in collaboration with Mathmatec Corporation, has developed an arithmetic processing IP core for MP3 decoders that uses less than 10% of the power required for conventional general software processing. By optimising circuits with original Murata architecture, used in conjunction with the Spinor circuit compression technology developed by Mathematec Corporation, Murata has succeeded in achieving a circuit size and power consumption level that ranks among the smallest and lowest ever to have been developed.

The IP core is a very small circuit of only 32 000 gates plus 76kbit of RAM, consuming just 0.35mW (measured for 44.1kHz 128 kbps Stereo output, with the core implemented in IBM9SFLP process). Typical power consumption for conventional software processing techniques is approximately 4mW based on Murata's research. Its clock rate is less than 20MHz since real time decoding is possible at 6MHz. The core is compliant with relevant MP3 (ISO/IEC11172-3, ISO/IEC13818-3) standards.

The IP core will be made available to customers as a synthesisable soft macrocell. In addition to providing hard macrocells optimised for specific processes, Murata will also address customers' unique requirements.