Synopsys has announced a suite of features for its 3200 Mbps DesignWare DDR4 IP to expand memory capacity for high-performance cloud computing systems while improving reliability, accessibility and serviceability (RAS). The DDR IP supports advanced error correcting code (ECC), which can correct all DRAM failures within a device to enable replacement of defective DIMMs without data loss.
In addition, support for high-capacity DDR4 LRDIMM and DDR4 3D Stacked (DDR4-3DS) DRAM with 16 ranks of memory expands capacity by up to 400% compared to the previously supported four ranks, without reducing performance. The IP includes the industry's only embedded calibration processor, which can train the system at power-up to improve design margin and signal integrity. The calibration processor can also train up to four active operating modes to manage rapid power and frequency requirement changes. Synopsys' DDR4 Controller and PHY IP solution enables cloud and virtualised server environments to support larger numbers of clients simultaneously and quickly solve complex computation problems.
"As the DRAM requirements for networking, storage and security applications increase, efficient access to more memory is critical," said Matthias Buchner, director of compute and networking marketing at Micron Technology, Inc. "System architects are dramatically improving their products' reliability, capacity and performance with SDRAM DDR4 from Micron. Synopsys' DDR4 IP further expands accessible memory capacity without degrading performance, enabling designers to increase their systems' overall capabilities."
The DesignWare uMCTL2 Memory Controllers and uPCTL2 Protocol Controllers support DDR4/3 and LPDDR4/3 standards and offer strong RAS features. The controllers' DDR4 command/address (CA) parity and write cyclic redundancy check (CRC) with retry features provide data and command/address integrity, allowing the system to recover from a command or address error by returning to the last known good state and retrying the failed command. New advanced ECC within the controllers uses modified Reed-Solomon coding to correct up to four consecutive data bits in each word, as may be required during a complete failure of one DRAM device connected to a SoC.
To assist with system-level optimisation, the new embedded calibration processor within the DesignWare DDR4/3 PHY facilitates design-for-test (DFT) functionality by generating two-dimensional read and write data eyes for every bit of the bus that can be captured by the IP. Up to four active operating states are trained at boot time and maintained as voltages and temperatures change. Each active operating state can have unique frequencies, equalization settings and termination settings to allow the host SoC to change its operating mode based on the power and frequency requirements.
"Memory access has become an important design consideration in high-performance storage, computing and cloud server applications," said John Koeter, vice president of marketing for IP and prototyping at Synopsys. "By providing differentiated functionality, including support for high-capacity LRDIMM, advanced ECC and embedded calibration, Synopsys enables designers to significantly increase the memory capacity of their systems without sacrificing the maximum operating frequency."
The new features for the DesignWare uMCTL2 Memory Controllers, DesignWare uPCTL2 Protocol Controllers and DesignWare DDR4/3 PHYs are available now. In addition to the controllers and PHYs, Synopsys' complete DDR4 IP solution includes IP subsystems, IP prototyping kits, IP software development kits, verification IP, and performance analysis using DesignWare DDR Explorer and Platform Architect MCO.