Synopsys announced that its DesignWare SuperSpeed USB 3.0 IP has surpassed 40 SoC design wins and more than 30 customer licensees worldwide. Because Synopsys' DesignWare USB 3.0 Digital Core and PHY IP has been broadly adopted by leading semiconductor companies targeting a variety of applications and process technologies, designers can be confident the IP is silicon-proven and can lower their SoC integration risk.

Synopsys, Inc.announced a licensing agreement enabling Synopsys to distribute ARM's Fast Models and create models of ARM Cortex Series processors. Designers will be able to accelerate embedded software development for ARM technology-based designs by up to nine months by creating virtual prototypes using ARM models with Synopsys' DesignWare TLM, SystemC TLM Libraries and Virtualizer™ tool set. ARM Fast Models and other ARM transaction-level mode...

Synopsys, Inc. announced the availability of enhancements to its CODE V optical design and analysis software, acquired as part of Synopsys' acquisition of Optical Research Associates. CODE V 10.4 delivers enhancements to its Beam Synthesis Propagation tool that enable optical designers to model and analyze diffraction effects in an optical system with increased flexibility, speed and accuracy. These enhancements are particularly useful for evalua...

Synopsys, Inc. announced availability of the latest release of its Synplify Pro and Synplify Premier FPGA synthesis tools. The new Synplify tool release enables engineers to build higher reliability into their FPGA designs through a new feature that provides automated creation and preservation of error-correction logic, including safe finite-state machines (FSMs). Additionally, an enhanced interface for the tool allows designers to track progress...

Synopsys, Inc. announced advances in its Galaxy Implementation Platform with the availability of its unified solution for mixed-signal designs. The new unified solution provides seamless integration between IC Compiler physical implementation and the Galaxy Custom Designer solution, allowing design teams to easily move between digital and custom implementation flows while maintaining design data integrity. The unified solution accelerates the des...

Synopsys, Inc. announced new capabilities in TetraMAX ATPG and Yield Explorer that decrease the time, effort and cost of deploying a volume diagnostics flow and speed-up yield ramp. When yield has not yet reached acceptable levels during initial manufacturing phases, IC product teams must quickly identify and fix the dominant causes of yield loss. Synopsys' enhanced volume diagnostics solution cross-correlates large volumes of data from design, f...

Synopsys, Inc. announced that its DesignWare STAR Memory System has shipped in one billion chips from semiconductor manufacturers worldwide, reinforcing its status as a trusted test and repair solution for embedded memories. The STAR Memory System is an advanced built-in-self-test solution that provides automated pre- and post-silicon memory test, debug and diagnostic capabilities. The automated BIST insertion and advanced repair features reduce ...

Synopsys, Inc announced that John Chilton, senior vice president of marketing and corporate development, will speak at the 2011 Deutsche Bank Technology Conference in Las Vegas, on Sept. 14, 2011.

Synopsys, Inc announced today that it has completed the acquisition of nSys Design Systems Private Limited (nSys). With this acquisition, Synopsys is increasing its investment in VIP technology to address the growing verification challenges designers face as they create more and more complex systems on chips (SoCs) to serve the demand for 'smart' electronics. The terms of the deal, structured as an acquisition of substantially all the assets and ...

Synopsys, Inc. and Achronix Semiconductor today announced a multi-year extension of their OEM agreement for Synopsys FPGA synthesis tools. The agreement continues to make Synopsys’ FPGA logic synthesis technology available to Achronix customers by expanding support of Synopsys’ Synplify Pro(r) software to Achronix’s latest generation of FPGAs, the 22 nanometer Speedster22i(tm) FPGA Platform. Achronix intends to deliver a Speedster22i FPGA-o...

Synopsys today announced University of Rochester students Bin Ma and Dustin Moore are the winners of the 2011 Robert S. Hilbert Memorial Optical Design Competition. The competition was created in 2000 by Optical Research Associates (ORA®), now the Optical Solutions Group at Synopsys, and was named in honor of ORA's former president and chief executive officer Robert S. Hilbert. The annual competition is open to students in North America working ...

Synopsys has announced it will report results for the third quarter fiscal year 2011 on Wednesday, Aug. 17, 2011, after the market close

Synopsys announced the availability of enhancements to its LightTools illumination design and analysis software, acquired as part of Synopsys' acquisition of Optical Research Associates (ORA). LightTools 7.2 delivers features that will help users graphically analyze simulation results, compute important metrics when designing for the lighting industry, iteratively design with CAD software and improve the efficiency of luminaire and solar designs....

Synopsys has announced that Ricoh Company Ltd., a global leader in imaging devices and industry products, has adopted Processor Designer for custom digital signal processor design. Ricoh's Core Technology Research and Development team designed their latest DSP in only five months, without needing DSP design expertise. Processor Designer automated the custom processor design process by generating both a software development tool flow and optimized...

Virtualizer Accelerates Software Development Schedules by Up to Nine Months with Lower Engineering Effort

Synopsys announced the appointment of Chrysostomos L. Max Nikias to its Board of Directors, effective July 11, 2011. Dr. Nikias is the current President of the University of Southern California (USC), a position he has held since August 2010, and holds the Robert C. Packard President's Chair and the Malcolm R. Currie Chair in Technology and the Humanities.

Synopsys today announced IC Compiler-Advanced Geometry, a new configuration of its market-leading IC Compiler physical design product. IC Compiler-Advanced Geometry targets design support for double-patterning technology (DPT), which has emerged as a key requirement for the next generation of silicon technology at 20 nanometers (nm) and imposes strict constraints on placement, routing and physical verification.

Synopsys announced that its design enablement collaboration with Samsung Electronics, Co., Ltd., a global leader in advanced semiconductor solutions, has achieved a critical milestone with the successful tapeout of the first 20-nanometer (nm) test chip based on Samsung's High-k metal gate (HKMG) process technology. The test chip was implemented using Synopsys' Galaxy™ Implementation Platform, including the Design Compiler® synthesis, IC Compil...

Synopsys, Inc. a world leader in software and IP for semiconductor design, verification and manufacturing, today announced that it has collaborated with GLOBALFOUNDRIES to jointly develop, validate, support and distribute interoperable process design kits (iPDKs) for GLOBALFOUNDRIES' mainstream and advanced process technologies. The GLOBALFOUNDRIES 65-nanometer (nm) iPDKs are available now with additional iPDKs planned for delivery later in 2011....

DesignWare AEON Embedded Non-Volatile Memory IP Improves Electrical Performance and Lowers Integration Risk for Wireless and Analog SoC Designs - Synopsys, Inc. , a world leader in software and IP for semiconductor design, verification and manufacturing, today announced the immediate availability of DesignWare® AEON® Non-Volatile Memory (NVM) IP for multiple 180-nanometer (nm) process technologies. The DesignWare AEON NVM IP products include fe...