Cadence Design Systems

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Cadence Design Systems articles

Displaying 21 - 40 of 397

Verification platform delivers 2X design compilation capacity

Verification platform delivers 2X design compilation capacity
The verification market is growing as it represents more and more of the costs of chip design, and as processes move deeper into sub-micron territory, costs could be up to 80% for designers using 5nm nodes. To meet this challenge Cadence Design Systems has unveiled the third generation of its Jasper Gold Formal Verification Platform, featuring machine learning technology and core formal technology enhancements.
8th May 2019

Design tools certified for 3D chip stacking technology

Design tools certified for 3D chip stacking technology
TSMC has certified Cadence Design System’s design solutions for the new TSMC System-on-Integrated-Chips (TSMC-SoIC) 3D advanced chip stacking technology, which integrates heterogenous chips—including logic ICs and memory—that are fabricated on different process nodes onto a single chip stack for a subsequent packaging process.
24th April 2019

Memory IP subsystem wins ISO 26262 ASIL C certification

Good news for Cadence Design Systems is that its LPDDR4/4X memory IP subsystem, utilising TSMC’s 16nm FinFET Compact (16FFC) technology, has achieved ISO 26262 ASIL C certification from SGS-TÜV Saar. The certification confirms that the Cadence IP is complete and ready for use by customers creating advanced systems-on-chip (SoCs) for advanced driver assistance systems (ADAS) and L3/L4 autonomous driving applications.
23rd April 2019


Parasitic extraction tools enabled for gate-all-around technology

Parasitic extraction tools enabled for gate-all-around technology
It has been announced by Cadence Design Systems that the Cadence Innovus Implementation System and Quantus Extraction Solution are now enabled for the Samsung Foundry Gate-All-Around (GAA) technology. The Cadence tools have been confirmed to meet Samsung Foundry’s technology requirements, which lets customers who produce high-end products for the mobile, networking, server and automotive markets leverage GAA technology.
4th April 2019

Verification IP for USB4 enables early adoption

Verification IP for USB4 enables early adoption
The availability of the industry’s first Verification IP (VIP) in support of the recently announced USB4 standard has been announced by Cadence Design Systems. The Cadence VIP for USB4 enables engineers to develop standard-compliant system-on-chip (SoC) designs, completing functional verification of the design with less effort and greater assurance that the SoC will operate as expected.
27th March 2019

Accelerating delivery of advanced 3D flash memory devices

Accelerating delivery of advanced 3D flash memory devices
Cadence Design Systems announced that Toshiba Memory Corporation has successfully used the Cadence CMP Process Optimiser, a model calibration and prediction tool that accurately simulates multi-layer thickness and topography variability for the entire layer stack, to accelerate the delivery of its advanced 3D flash memory devices. With the Cadence solution in place, Toshiba Memory Corporation achieved 95.7% accuracy to silicon.
18th March 2019

LPDDR5 IP solution targets AI, IoT applications

Early availability of the complete, silicon-proven Cadence Denali Gen2 IP for LPDDR5/4/4X in TSMC’s 7nm FinFET process technology has been announced by Cadence Design Systems. Offering up to 1.5X faster bandwidth than the fastest speed of LPDDR4 and LPDDR4X, the LPDDR5 standard enables high bandwidth with low power consumption, making it well suited for mobile computing, AI, IoT, cryptocurrency mining and automotive applications.
8th March 2019

embedded world: DSP lifts radar/lidar and 5G performance

embedded world: DSP lifts radar/lidar and 5G performance
Boosting performance by up to 10X for Automotive Radar/Lidar and up to 30X for 5G communications the Cadence Tensilica ConnX B20 DSP IP becomes the highest-performing DSP in the ConnX family. Based on a deeper processor pipeline architecture, this DSP provides a faster and more power-efficient solution for the automotive and 5G communications markets, including next-generation radar, lidar, vehicle-to-everything (V2X), user equipment (UE)/infrastructure and IoT applications.
26th February 2019

EDA tool vendor selected for advanced node chip design

EDA tool vendor selected for advanced node chip design
It has been announced that GLOBALFOUNDRIES (GF), has chosen Cadence Design Systems as the primary EDA tool vendor for use in Avera Semi, a GF subsidiary, for advanced node chip design projects. The Avera Semi engineering team has reportedly come to rely on the features, capacity, speed and scalability of the Cadence digital and signoff, system and verification, custom IC and PCB design and analysis tools and flows.
18th February 2019

Timing signoff tools enables 400Gbps PAM4 SoC on 16FF process

Timing signoff tools enables 400Gbps PAM4 SoC on 16FF process
It has been announced by Cadence Design Systems that MaxLinear has used Cadence timing signoff tools to successfully deliver the MxL935xx Telluride device, a 400Gbps PAM4 system on chip (SoC) using 16FF process technology. The Cadence Quantus Extraction Solution and Tempus Timing Signoff Solution were key enablers of the on-time delivery of working silicon for MaxLinear.
12th December 2018

Next-generation cloud datacenter infrastructure accelerated

Next-generation cloud datacenter infrastructure accelerated
Cadence Design Systems, has unveiled the industry’s first silicon-proven, long-reach 112G SerDes IP in seven nanometre. The Cadence seven nanometre 112G PAM-4 SerDes IP delivers industry-leading power, performance and area (PPA) efficiency required to build high-port density networking products for next-generation cloud-scale and telco datacenters. 
26th November 2018

Cloud-Hosted Design Solution Achieves Industrial Software Competency Status

Cadence Design Systems Cloud-Hosted Design Solution has undergone rigorous technical validation and achieved Amazon Web Services Industrial Software Competency status. This recognizes the Cadence solution has demonstrated technical proficiency and proven customer success with electronic systems and semiconductor companies. The Cadence Cloud-Hosted Design Solution enables customers to increase the pace of product innovation while decreasing production and operational overhead by providing a turnkey cloud solution optimized for systems and semiconductor projects.
22nd October 2018

Cadence Achieves EDA Certification

Cadence announced its continued collaboration with TSMC to certify its design solutions for TSMC 5nm and 7nm+ FinFET process technologies for mobile and high-performance computing designs. As part of the collaboration, the Cadence digital, signoff and custom/analog tools have achieved the latest Design Rule Manual and SPICE certification for the TSMC 5nm and 7nm+ processes, and the corresponding process design kits are now available for download. Customers using Cadence’s implementation, signoff and custom/analog tools are already in production with 7nm+ projects, and there are multiple design projects underway with early 5nm customers.
22nd October 2018

Arm-based server development accelerated with collaboration

Arm-based server development accelerated with collaboration
A collaboration between Cadence Design Systems and Arm has been announced to enable high-performance computing (HPC) customers to execute bare metal pre-silicon verification compliance tests through the Arm Server Base System Architecture (SBSA) Compliance Suite.
19th October 2018

Verification suite enabled on Arm-Based HPC datacenters

Verification suite enabled on Arm-Based HPC datacenters
It has been announced by Cadence Design Systems, that the Cadence Verification Suite is now enabled for Arm-based high-performance computing (HPC) server environments. Through an industry ecosystem collaboration, software tools in the suite, include Xcelium Parallel Logic Simulation, and run on the Hewlett Packard Enterprise (HPE) Apollo 70 System.
19th October 2018

Cadence Launches New Tensilica DNA 100 Processor IP

Cadence Launches New Tensilica DNA 100 Processor IP
Cadence announce the Cadence Tensilica DNA 100 Processor IP, the first deep neural-network accelerator AI processor IP to deliver both high performance and power efficiency across a full range of compute from 0.5 TeraMAC (TMAC) to 100s of TMACs. As a result, the DNA 100 processor is well suited for on-device neural network inference applications spanning autonomous vehicles, ADAS, surveillance, robotics, drones, augmented reality /virtual reality, smartphones, smart home and IoT. The DNA 100 processor delivers up to 4.7X better performance and up to 2.3X more performance per watt compared to other solutions with similar multiplier-accumulator (MAC) array sizes.
18th October 2018

Process technologies to facilitate HPC design creation

Process technologies to facilitate HPC design creation
  The collaboration between Cadence Design Systems, and TSMC is set to continue, in order to certify Cadence’s design solutions for TSMC five nanometre and seven nanometre+ FinFET process technologies for mobile and high-performance computing (HPC) designs.
2nd October 2018

On-device applications covered by DNA AI processor

On-device applications covered by DNA AI processor
The Cadence Tensilica DNA 100 Processor IP, deep neural-network accelerator (DNA) AI processor IP delivers high performance and power efficiency across a full range of compute from 0.5 TeraMAC (TMAC) to 100s of TMACs. As a result, the DNA 100 processor is well suited for on-device neural network inference applications spanning autonomous vehicles (AVs), ADAS, surveillance, robotics, drones, augmented reality (AR) /virtual reality (VR), smartphones, smart home and IoT.
21st September 2018

Ecosystem connects manufacturers to ensure design manufacturability

Ecosystem connects manufacturers to ensure design manufacturability
Cadence Design Systems has announced that it has launched a broad ecosystem with nine initial PCB manufacturing partners to enable customers to easily get the partners’ technology files they need to ensure PCB design manufacturability early in the design process. This reduces rework, shortens design cycles, and accelerates new product introduction.
7th September 2018

Digital tool suite achieves GLOBALFOUNDRIES 22FDX

Digital tool suite achieves GLOBALFOUNDRIES 22FDX
It has been announced by Cadence Design Systems that its full-flow digital tool suite has achieved certification for the GLOBALFOUNDRIES (GF) 22FDX process technology. The GF certification process was completed using the Cadence Tensilica Fusion F1 DSP, which targets Internet of Things (IoT) and wearables applications.
31st August 2018


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