How Adeia is solving semiconductor's toughest thermal challenge

Adeia is a US-based technology licensing and R&D company specialising in semiconductor and media technologies. With a portfolio spanning thousands of patents, the company works at the leading edge of advanced packaging, interconnect, and thermal management.

As the demands of artificial intelligence place ever greater pressure on hardware performance, Adeia’s semiconductor result. engineering team, led by SVP Laura Mirkarimi, is tackling some of the industry’s most pressing challenges head-on.

Here, Mirkarimi outlines the company’s R&D approach and introduces RapidCool – Adeia’s award-winning direct-to-chip liquid cooling technology.

The AI era and its demands on hardware

During this pivotal phase of the AI era, large language models are reshaping the demands placed on hardware and system architectures for high performance compute. Several interconnected trends are emerging as a result.

Wide I/O and massively parallel processing are pushing pitch scaling of the interconnect to its limits, making optimisation of interconnect performance increasingly essential. At the same time, rising compute density and IC power densities have made thermal management an imperative rather than an afterthought.

The evolution of package architecture – from 2.5D through to 3D and 3.5D configurations – compounds these thermal challenges, driving maximum temperatures higher within the module. Addressing this requires co-optimisation of the thermal solution across both package assembly considerations and IC power densities.

“To meet these demands, we are advancing hybrid bond interconnect technology, developing innovative methods and structures that enable scaling, higher performance, and easier integration of multi-die architectures. Compared to conventional microbump approaches, hybrid bond delivers meaningful improvements in thermo-electric performance within die stacks,” said Mirkarimi.

Introducing RapidCool

Complementing this work, Adeia has developed a direct-to-chip liquid cooling solution for the next generation of chips – a technology it calls RapidCool.

Adeia’s RapidCool technology is a singular direct-to-chip liquid cooling solution designed for high performance semiconductors. It works by bonding a silicon cold plate directly to chips alongside an integrated manifold – a patented approach that delivers approximately 70% reduction in thermal resistance. Built from the ground up to address the demanding thermal challenges posed by advanced processors and memory, it is particularly well-suited to multichip architectures.

The process begins by examining the heatmap of packages and multichip modules to identify hot spots. It then applies the simulation protocol to create digital twins, which inform the development of custom thermal management solutions tailored to each application.

RapidCool comprises two complementary components – the cold plate or heat sink, and the integrated manifold – which together provide multiple levers for improving the thermal performance of the module while satisfying system-level requirements such as coolant flow rate to the rack and acceptable pressure drop.

A unique dual-component architecture

While the concept of silicon microchannel cooling is not entirely new – a similar idea was proposed by Tuckerman and Pease as far back as 1980 – Adeia’s approach differs substantially from that original work, which was ultimately held back by integration challenges and system incompatibility stemming from prohibitively large pressure drops of around 400 psi.

“Our cold plate/heat sink and manifold approach is unique in that it is significantly easier to integrate with standard semiconductor manufacturing processes. Additionally, we have found a variety of ways to improve thermal performance while meeting the system level requirements to improve the overall energy efficiency resulting in cooler-running modules,” notes Mirkarimi.

Eliminating TIM resistance

Thermal interface materials (TIMs) will continue to play an important role in transferring heat from silicon to cold plates and heat sinks, which are typically metal-based systems. However, at power densities of around 2W/mm² and beyond, this approach becomes increasingly inadequate.

Addressing this limitation requires looking at the full picture of thermal resistance between the coolant inlet and the chip. This resistance is a function of IC resistance, TIM resistance, and cold plate resistance combined. By eliminating TIM resistance entirely, overall thermal resistance is reduced and maximum junction temperatures are lowered – Adeia’s measurements show an 80% resistance reduction achieved through TIM elimination.

Reliability is equally important. Performance failures in the field are frequently linked to TIM reliability issues, making a solution that removes this failure mode highly significant for total cost of ownership at the data centre level.

The road to adoption

The most likely initial adoption of RapidCool will be in high performance compute modules for the data centre market.

Mirkarimi notes that predicting the precise timing of that adoption is difficult for a number of reasons.

“Data centres tend to stick with incumbent technologies until they can no longer meet needs.

“Our solution has several new concepts that fit nicely into advanced packaging manufacturing; however, these specific processes and integration schemes that we have demonstrated are not yet standard processes in high volume manufacturing (HVM) right now,” she said.

This article originally appeared in the May’26 magazine issue of Electronic Specifier Design – see ES’s Magazine Archives for more featured publications.