Memory tester integrates burn-in and memory-cell testing

With the advent of 5G technology, worldwide DRAM bit-based consumption is expected to approximately double in the next three years.

This increase is being driven primarily by growth in the data-processing and mobile-communication market segments, with data centres requiring more memory and smart-phone functionality expanding to include higher resolution, foldable capability and multi-camera designs.

As the average selling prices for memory ICs continue to shrink, semiconductor manufacturers need ways to reduce testing costs while increasing production volumes.

Advantest’s newest tester helps to accomplish this with its superior efficiency. In production environments, the H5620 can test over 18,000 devices in parallel at 100-MHz frequencies and data rates up to 200 Mbps. It is adaptable for factory automation and supports a wide temperature range of -10° C to 150° C with a dual-chamber structure featuring individual thermal-control stability.

In addition, the new system can reduce customers’ capital expenditures and save floor space by combining legacy memory-cell testing with the burn-in test process in memory production facilities.

“By delivering high productivity at a low cost of test, this memory tester raises the bar for evaluating today’s newest DRAMs,” said Takeo Miura, vice president of the Memory ATE Business Group at Advantest.

The H5620 runs on the FutureSuite operating system with its versatile tool set. This software ensures that the tester can be easily integrated with legacy memory test systems from Advantest. In addition, assistance with program coding, debugging, correlation and maintenance is available from Advantest’s global support network.

The new H5620 tester has begun shipping to customers and the H5620ES engineering model will be ready by the second quarter of this calendar year.

Picture shows the H5620 tester