JTAG platform simplifies chiplets test method
A newly enhanced version of ASSET InterTech’s ScanWorks JTAG-based platform of hardware debug, validation and test tools allows engineers to more easily test the device interconnects between silicon ‘chiplets’ in multi-die packages.
It also shortens the time to program flash memories from hours to minutes.
For many years, ScanWorks’ JTAG tools have been used to test interconnects between integrated circuit devices on circuit boards.
With these recent enhancements, ScanWorks now can quickly generate test patterns in the Standard Test Interface Language (STIL) that can be applied by chip-level automatic test equipment (ATE) to test for shorts and opens between chiplets.
“Previously, implementors of multi-die packages would manually write their own ad-hoc test scripts to generate the interconnect test patterns that would then be converted into STIL,” said Michael Johnson, ASSET’s product manager of ScanWorks. “But now, ScanWorks can take the netlist for such a package and directly generate the STIL test patterns to be applied by an ATE system, thus providing a simplified turnkey and automated test authoring solution for chiplets in multi-die packages. As a basis for on-board testing, suppliers of this type of package can provide the ScanWorks project used to generate the STIL patterns for ATE testing to board designers and contract manufacturers who are incorporating the package into their end products. This provides a complete end-to-end test and validation solution, another value point for the chiplet and multi-die package supplier.”
Greater integration of the ScanWorks FPGA-based Flash Programming (FFP) tool has simplified its use.
Instead of launching FFP’s Embedded Test Generator (ETG) separately, it is now implemented within the design module of ScanWorks, reducing the number of steps and shortening the time it takes to start using FFP.
Once deployed, FFP is able to reduce the programming times for flash memory devices from hours to minutes.
The FPGA suppliers supported by the ScanWorks’ FFP tool are Intel (including Altera), Microchip Technology (including Microsemi) and Xilinx .
Once a small test/programming agent is embedded into the on-chip RAM memory of an on-board System-on-a-Chip (SoC), ScanWorks’ Processor-based Functional Test/Programming (PFx) tool can perform fast programming routines, run functional tests on the devices and I/O buses on a circuit board, and configure or test DDR memories.
Recent enhancement of the PFx tool offers greater flexibility to the board designer because additional devices can be placed on the same boundary-scan chain that connects the SoC to ScanWorks.
The SoC families that are supported by the PFx tool include the i.MX6 from NXP, and the Zynq7000 and Zynq UltraScale+ from Xilinx.
ASSET is a member of the partner programs of each of these companies.
The new version of ScanWorks (Version 4.8) is available now from ASSET InterTech and its distributors.