ASSET InterTech Articles
JTAG platform simplifies chiplets test method
A newly enhanced version of ASSET InterTech’s ScanWorks JTAG-based platform of hardware debug, validation and test tools allows engineers to more easily test the device interconnects between silicon ‘chiplets’ in multi-die packages.
Support slashing flash programming times
Newly released support for Microsemi FPGAs and SoCs on ASSET InterTech’s ScanWorks can decrease programming times for SPI flash memory devices to the point where inline programming on the assembly line will not disrupt the manufacturing beat rate. ASSET InterTech is a leading supplier of JTAG-based software and hardware debug, validation and test tools.
Fast flash programming tool eliminates production delays
Newly released support for Microsemi FPGAs and SoCs on ASSET InterTech’s ScanWorks can dramatically decrease programming times for SPI flash memory devices to the point where inline programming on the assembly line will not disrupt the manufacturing beat rate.
Ethernet controller features faster test clock
Because of its expanded internal memory, a new Ethernet controller for ASSET InterTech’s ScanWorks platform can program larger data images and process test operations faster. The Remote Instrumentation Controller, designated the RIC-1400, is a direct replacement for the RIC-1000
Platform opens two routes to DDR4 testing
Engineers designing with Double Data Rate 4 (DDR4) memory devices can quickly deploy tests for shorts and opens on control, address and data lines with the boundary scan test (BST) tools of ASSET InterTech’s ScanWorks platform for fast test and programming.
Faster flash programming enhances production throughput
Faster test and programming tools from ASSET InterTech will accelerate the production of system designs based on Xilinx Zynq UltraScale+ Multiprocessor SoCs (MPSoC). These tools for the ScanWorks platform for fast test and programming take advantage of a target agent running out of a small amount of on-chip memory associated with one of the Arm Cortex cores in the Zynq UltraScale+ MPSoC.
Test and programming tools hasten SOC systems design
Faster test and programming tools from ASSET InterTech will accelerate development and production cycles for designs based on Xilinx Zynq-7000 SoCs. These new tools, which join the ScanWorks platform for fast test and programming, take advantage of a target agent running out of a small amount of on-chip memory associated with one of the Arm Cortex cores in the Zynq-7000 SoC.
Companies collaborate on boundary-scan testing
Circuit Check is collaborating with ASSET InterTech to more closely integrate ASSET’s ScanWorks boundary-scan test tools with CCI’s flexible, configurable functional test systems, the CCI 1000 Series Configurable ATE and CCI 6000 Series Rotary Handler.
Debugger supports all Intel’s embedded trace facilities
SourcePoint from ASSET InterTech is the first debugger to take advantage of all of the trace facilities embedded in several of Intel’s most advanced processors, including those based on the microarchitecture codenamed Skylake for 6th Generation Core and Intel Xeon processor E3 v5, as well as several other microarchitectures not yet made public.
PCT tool performs more tests at high speed
The newly enhanced processor-controlled test (PCT) tool on ASSET InterTech’s ScanWorks platform can perform structural and functional test, as well as diagnostics, in one pass and still achieve the high test speeds required on manufacturing lines. based on embedded instrumentation.
Asset's acceleration aids Cornwall's waste-to-energy power plant
Asset expertise and Weholite technology are helping Cornwall to create a showcase waste-to-energy power plant to replace the county’s shrinking landfill capacity. When complete, the new Cornwall Energy Recovery Centre (CERC) near the village of St Dennis will turn 240,000 tonnes of household waste a year into enough electricity to power 21,000 local homes.
Software debugger simplified to USB3
A new system controller for ASSET InterTech’s SourcePoint hardware-assisted software debug platform allows engineers to begin software debug immediately by offering a fast and easy way to connect SourcePoint to Intel-based target platforms that support Direct Connect Interface (DCI).
eBook throws light on new JTAG standard
A new eBook from ASSET InterTech explains how a relatively new industry standard, IEEE 1687 Internal JTAG (IJTAG), provides critical capabilities not found in older standards, such as the IEEE 1149.1 boundary-scan standard, commonly referred to as JTAG, and the IEEE 1500 embedded core test (ECT) standard.
Data mining tool streamlines serdes validation
The HSIO Validation Assistant (HVA), a new data mining tool for ASSET InterTech’s ScanWorks platform, automatically analyses a database of signal integrity test data and quantifies the risk associated with potential design flaws or poorly performing devices on a system’s high-speed input/output (HSIO) buses.
IJTAG interoperability demos at ITC in Anaheim
At the International Test Conference (ITC) in Anaheim, ASSET InterTech and Cadence Design Systems are demonstrating the interoperability of their IEEE 1687 Internal JTAG (IJTAG) tools, which enable the re-use of embedded intellectual property (IP) both internally on chips and externally onto system boards.
E-book helps software engineers track bugs faster
Software engineers can spend days or weeks tracking down bugs in complex software for multicore systems-on-a-chip (SoC), often delaying new product introductions. A new eBook by ASSET InterTech explains how developers can take advantage of both trace and static analysis tools for greater insight into code execution and to identify root causes faster.
In-system memory programming cut from minutes to seconds
Programming memory in-system, or after the devices have been soldered to a circuit board, is the most efficient method, but the challenge for design and manufacturing engineers has always been the slow speeds of the process. Now, enhancements to ASSET InterTech’s ScanWorks platform for embedded instruments can speed up in-system programming by a factor of 1,000, reducing programming times from 10 or more minutes to one or two seconds.
Debug platform captures "an eternity in the boot process"
The first debug platform to provide real insight from Intel Trace Hub to debug the Unified Extensible Firmware Interface (UEFI) that initialises system hardware and software has been introduced by Asset InterTech. SourcePoint can tap into both hardware and software sources of trace information to show engineers the exact code execution flow and system message execution information.
e-Book explains faster flash programming
New faster methods for the in-system programming of onboard flash as well as I2C and SPI memory are explained in a new eBook published by ASSET InterTech. In-system programming has many advantages over standalone programming stations, but, until now, its programming speed has presented a challenge for design and production engineers.
eBook explains latest IEEE IJTAG standard
The IEEE 1687 Internal JTAG (IJTAG) standard enhances the portability and re-use of embedded instrument intellectual property (IP) and defines a dynamically scalable on-chip network for instrumentation IP. A new eBook published by ASSET InterTech explains these innovations and others such as managing power domains with IJTAG, enabling instrument concurrence and retargeting test vectors.