GaN is expected to play a key part in everything from high-speed communication systems to power electronics needed for cutting-edge data centres. But its cost and the specialisation needed to incorporate it into conventional electronics have hindered its use in commercial applications.
With this new method from MIT – building many tiny transistors onto the surface of a GaN chip, cutting out each individual transistor, and then bonding the necessary number of transistors onto a silicon chip using a low-temperature process – all of that is hoped to be in the past.
The cost remains minimal as only a tiny amount of GaN material is added to the chip, but the resulting device can receive a significant performance boost from compact, high-speed transistors. Also, by separating the GaN circuit into discrete transistors that can be spread over the silicon chip, the new technology is able to reduce the temperature of the system.
The researchers used this process to fabricate a power amplifier, a core component in mobile phones, that achieves higher signal strength and efficiencies than devices with silicon transistors. In a smartphone, this could mean improved call quality, wireless bandwidth, connectivity, and an extended battery life.
Because this method fits into standard procedures, it could improve electronics today as well as future technologies. Looking forward, the new integration scheme could enable quantum applications, as GaN performs better than silicon at the cryogenic temperatures needed for quantum computing.
“If we can bring the cost down, improve the scalability, and, at the same time, enhance the performance of the electronic device, it is a no-brainer that we should adopt this technology. We’ve combined the best of what exists in silicon with the best possible gallium nitride electronics. These hybrid chips can revolutionise many commercial markets,” explained Pradyot Yadav, an MIT graduate student and lead author of a paper on this method.
He is joined on the paper by fellow MIT graduate students Jinchen Wang and Patrick Darmawi-Iskandar; MIT postdoc John Niroula; senior authors Ulrich L. Rohde, a visiting scientist at the Microsystems Technology Laboratories (MTL), and Ruonan Han, an associate professor in the Department of Electrical Engineering and Computer Science (EECS) and member of MTL; and Tomás Palacios, the Clarence J. LeBel Professor of EECS, and director of MTL; as well as collaborators at Georgia Tech and the Air Force Research Laboratory. The research was recently presented at the IEEE Radio Frequency Integrated Circuits Symposium.
Swapping transistors
GaN is the second most widely used semiconductor in the world, after silicon, with properties that make it ideal for applications including lighting, radar systems, and power electronics.
The material has been around for decades, and to access its maximum performance, it is important for chips to be made of GaN to be connected to digital chips made of silicon – also known as CMOS chips.
To facilitate this, some integration methods bond GaN transistors onto a CMOS chip by soldering the connections, but this subsequently limits how small the GaN transistors can be. The smaller the transistors, the higher frequency at which they work.
Other methods integrate an entire GaN wafer on top of a silicon wafer, but using this much material is expensive, particularly as GaN is only needed in a few tiny transistors. The rest of the material in the GaN wafer is wasted.
“We wanted to combine the functionality of GaN with the power of digital chips made of silicon, but without having to compromise on either cost of bandwidth. We achieved that by adding super-tiny discrete gallium nitride transistors right on top of the silicon chip,” said Yadav.
The new chips are the result of a multistep process: a tightly packed collection of miniscule transistors is fabricated across the entire surface of a GaN wafer; using fine laser technology, they cut each one down to the size of the transistor (240 by 410 microns); each transistor is fabricated with tiny copper pillars on top, which are used to bond directly to the copper pillars on the surface of a CMOS chip.
Copper to copper bonding can be achieved at temperatures less than 400 degrees celsius, which means either material is preserved.
Current GaN integration techniques require bonds that utilise gold, an expensive material that needs much higher temperatures and stronger bonding forces than copper. Since gold can contaminate the tools used in most semiconductor foundries, it typically requires specialised facilities to do this.
“We wanted a process that was low-cost, low-temperature, and low-force, and copper wins on all of those related to gold. At the same time, it has better conductivity,” added Yadav.
A new tool
To enable the new integration process, the researchers created a specialised tool that can integrate the tiny GaN transistor with silicon chips. The tool uses a vacuum to hold the dielet as it moves on top of a silicon chip, zeroing in on the copper bonding interface with nanometer-level precision.
They also used advanced microscopy to monitor the interface and when the dielet is in the right position, apply heat and pressure to bond the GaN transistor to the chip.
“For each step in the process, I had to find a new collaborator who knew how to do the technique that I needed, learn from them, and then integrate that into my platform. It was two years of constant learning,” Yadav explained.
Once the researchers had nailed the fabrication process, they demonstrated it by developing power amplifiers, which are radio frequency circuits that boost wireless signals.
These devices achieved higher bandwidth and better gain than devices made with traditional silicon transistors. Each compact chip has an area of less than half a square millimetre.
Because the silicon chip they used in their demonstration is based on Intel 16 22nm FinFET state-of-the-art metallisation and passive options, they were also able to incorporate components often used in silicon circuits, such as neutralisation capacitors. This significantly improved the gain of the amplifier, bringing it one step closer to enabling the next generation of wireless technologies.
“To address the slowdown of Moore’s Law in transistor scaling, heterogeneous integration has emerged as a promising solution for continued system scaling, reduced form factor, improved power efficiency, and cost optimisation,” said Atom Watanabe, a research scientist at IBM who was not involved with this paper. “Particularly in wireless technology, the tight integration of compound semiconductors with silicon-based wafers is critical to realising unified systems of front-end integrated circuits, baseband processors, accelerators, and memory for next-generation antennas-to-AI platforms.
“This work makes a significant advancement by demonstrating 3D integration of multiple GaN chips with silicon CMOS and pushes the boundaries of current technological capabilities.”
