Stacked CMOS imaging sensor offers higher pixel performance
A fully-functional stacked CMOS imaging sensor, claimed to feature a smaller die footprint, higher pixel performance and better power consumption compared to traditional monolithic non-stacked designs, has been successfully demonstrated by ON Semiconductor. The company demonstrated the technology on a test chip with 1.1µm pixels, and will introduce it later this year.
To support both the pixel array and supporting circuitry, traditional sensor designs in a monolithic substrate process require separate die area. With 3D stacking technology, the pixel array and the supporting circuitry are manufactured on separate substrates and then stacked with connections between the two made with through silicon vias (TSVs). This allows the pixel array to overlay the underlying circuitry, resulting in a more efficient die floorplan. Improved pixel performance with lower noise levels and enhanced pixel response is enabled by the 3D stacking technology. To lower power consumption, the underlying circuitry can use more aggressive design rules. The smaller overall footprint make the sensor suitable for camera modules that integrate optical image stabilisation and additional data storage in the same module footprint.
“3D stacking technology is an exciting breakthrough that enhances our ability to optimise ON Semiconductor’s future sensors,” said Sandor Barna, Vice President of Technology, Image Sensor Group, ON Semiconductor. “This technology provides manufacturing and design flexibility to ensure continued performance leadership across our entire sensor product portfolio.”
ON Semiconductor will be demonstrating its latest image sensor technology at CES 2015, which takes place from 6th to 8th January.
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