Verification suite optimised to support Arm Cortex-A75
In order to support Arm Cortex-A75 and Cortex-A55 CPUs, based on Arm DynamIQ technology, and the Arm Mali-G72 GPU, the latest offerings from Arm for premium mobile, machine learning, and consumer devices, Cadence Design Systems has optimised its full-flow digital and signoff tools and the Cadence Verification Suite.
To accelerate the adoption of Arm’s latest processors, Cadence delivered new 7nm-ready Rapid Adoption Kits (RAKs) for the Cortex-A75 and the Cortex-A55 CPUs, which include the DynamIQ Shared Unit (DSU) that provides a shared level three cache between the CPUs, and a 7nm-ready RAK for the Mali-G72 GPU.
Customers are already using the complete digital and signoff flow and the Cadence Verification Suite to tape out complex systems-on-chip (SoCs) containing the latest Arm Cortex and Mali processors. The Cadence RAKs accelerate physical implementation, signoff, and verification of 7nm designs, allowing designers to deliver mobile and consumer devices to market faster. With the delivery of the new RAKs, Cadence is also providing specialised technical support for Arm IP implementation based on the deep collaboration between Arm and Cadence over many years.
The Cadence digital and signoff tools have been configured to provide optimal power, performance and area (PPA) results using the RAKs, which include scripts, an example floorplan, and documentation for Arm’s 7nm IP libraries. The comprehensive Cadence RTL-to-GDS flow incorporates the following digital and signoff tools in the RAKs:
- Innovus Implementation System: Statistical on-chip variation (SOCV) propagation and optimisation results in improved timing, power, and area closure for 7nm designs
- Genus Synthesis Solution: Register-transfer level (RTL) synthesis supports all the latest 7nm advanced-node requirements and provides convergent design closure using the Innovus Implementation System
- Conformal Logic Equivalence Checking (LEC): Ensures the accuracy of logic changes and engineering change orders (ECOs) during the implementation flow
- Conformal Low Power: Enables the creation and validation of power intent in context of the design, combining low-power equivalence checking with structural and functional checks to allow full-chip verification of power-efficient designs
- Tempus Timing Signoff Solution: Offers path-based, signoff-accurate and physically aware design optimisation, providing the quickest path to tapeout
- Voltus IC Power Integrity Solution: Static and dynamic analysis used during implementation and signoff ensures optimal power distribution
- Quantus QRC Extraction Solution: Fulfills all 7nm advanced-node requirements to ensure accurate correlation to final silicon.
“The Cortex-A75 and Cortex-A55 CPUs deliver distributed intelligence from edge-to-cloud, and pairing them with the Mali-G72 GPU enables consumers to experience stunning graphics efficiently across multiple devices,” said Nandan Nayampally, Vice President and General Manager, Compute Products Group, Arm. “By continuing to collaborate with Cadence on the delivery of new digital implementation and signoff RAKs along with optimisation of the Cadence Verification Suite, our mutual customers can quickly integrate and augment their differentiated solutions for next-gen devices.”
The Cadence Verification Suite that has also been optimised for Arm-based designs includes:
- JasperGold Formal Verification Platform: Enables IP and subsystem verification including formal proofs for Arm AMBA protocols
- Xcelium Parallel Logic Simulation: Provides production-proven multi-core simulation accelerating SoC development and validation of Arm-based designs
- Palladium Z1 Enterprise Emulation Platform: Includes hybrid technology that is integrated with Arm Fast Models for up to 50 times faster OS and software bring-up and up to ten times faster software-based testing in addition to Dynamic Power Analysis technology for low power
- Protium S1 FPGA-Based Prototyping Platform: Integration with the Palladium Z1 enterprise emulation platform combined with Arm DS-5 provides pre-silicon embedded software debug
- vManager Planning and Metrics: Metric-driven verification across the JasperGold platform, Xcelium simulation, Palladium Z1 platform and Cadence VIP solutions for Arm-based SoC verification convergence
- Perspec System Verifier: Provides software-driven use-case verification with the PSLib for Armv8 architectures, delivering up to ten times productivity improvement versus typical manual test development
- Indago Debug Platform: RTL design, testbench and embedded software debug capabilities synchronised with Arm CPUs for accurate combined views of hardware and software
- Cadence Verification Workbench: Integrates with Arm Socrates packaged Armv8 IP and VIP for fast SoC integration and UVM testbench assembly
- Cadence Interconnect Workbench: Provides fast performance analysis and verification of Arm CoreLink interconnect intellectual property (IP)-based systems in combination with Xcelium simulation, the Palladium Z1 platform, and Cadence Verification IP
- Verification IP Portfolio: Enables IP and SoC verification including Arm AMBA interconnect, supporting Xcelium simulation, the JasperGold platform, and the Palladium Z1 platform.
“We worked closely with Arm to optimise our advanced digital implementation and signoff solutions and our verification solutions for the new Arm CPUs and GPU so our customers can efficiently create 7nm mobile and consumer designs,” said Dr. Anirudh Devgan, Executive Vice President and General Manager of the Digital & Signoff Group and the System & Verification Group at Cadence. “Designers using the RAKs and the Cadence Verification Suite can benefit from improved PPA and reduced project times, while creating the most advanced Arm-based products.”